Add 'vendored_parsers/tree-sitter-vhdl/' from commit 'b863231107ef4471ad007a2405ef319875da5b4e'

git-subtree-dir: vendored_parsers/tree-sitter-vhdl
git-subtree-mainline: 2d61aefb84
git-subtree-split: b863231107
pull/618/head
Armin Brauns 2024-01-08 14:36:57 +07:00
commit 3de60c60ac
110 changed files with 389951 additions and 0 deletions

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[package]
name = "tree-sitter-vhdl"
description = "vhdl grammar for the tree-sitter parsing library"
version = "0.0.1"
keywords = ["incremental", "parsing", "vhdl"]
categories = ["parsing", "text-editors"]
repository = "https://github.com/tree-sitter/tree-sitter-vhdl"
edition = "2018"
license = "MIT"
build = "bindings/rust/build.rs"
include = [
"bindings/rust/*",
"grammar.js",
"queries/*",
"src/*",
]
[lib]
path = "bindings/rust/lib.rs"
[dependencies]
tree-sitter = "~0.20.10"
[build-dependencies]
cc = "1.0"

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MIT License
Copyright (c) 2020 Alexandre A. Muller
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.

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# tree-sitter-vhdl
Tree-sitter-vhdl is a VHDL parser for syntax highlighting.
## Missing features
- [x] VHDL-2008
- [ ] Protected tool directives
- [x] PSL-02
- [ ] LTL PSL Operators (not intended to be supported)
- [ ] OBE PSL Operators (not intended to be supported)
- [ ] VHDL-2019
Not listed features are implemented already.
## Notes
The parser accepts some illegal constructions to be able to provide precise
error highlight.
See `./tests/highlight/` and `./queries/highlights.scm` for a list of errors.
## References
* IEEE Std 1076-2008
* IEEE Std 1850-2005
* IEEE Std 1076-2019

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{
"targets": [
{
"target_name": "tree_sitter_vhdl_binding",
"include_dirs": [
"<!(node -e \"require('nan')\")",
"src"
],
"sources": [
"src/parser.c",
"bindings/node/binding.cc"
],
"cflags_c": [
"-std=c99",
]
}
]
}

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#include "tree_sitter/parser.h"
#include <node.h>
#include "nan.h"
using namespace v8;
extern "C" TSLanguage * tree_sitter_vhdl();
namespace {
NAN_METHOD(New) {}
void Init(Local<Object> exports, Local<Object> module) {
Local<FunctionTemplate> tpl = Nan::New<FunctionTemplate>(New);
tpl->SetClassName(Nan::New("Language").ToLocalChecked());
tpl->InstanceTemplate()->SetInternalFieldCount(1);
Local<Function> constructor = Nan::GetFunction(tpl).ToLocalChecked();
Local<Object> instance = constructor->NewInstance(Nan::GetCurrentContext()).ToLocalChecked();
Nan::SetInternalFieldPointer(instance, 0, tree_sitter_vhdl());
Nan::Set(instance, Nan::New("name").ToLocalChecked(), Nan::New("vhdl").ToLocalChecked());
Nan::Set(module, Nan::New("exports").ToLocalChecked(), instance);
}
NODE_MODULE(tree_sitter_vhdl_binding, Init)
} // namespace

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try {
module.exports = require("../../build/Release/tree_sitter_vhdl_binding");
} catch (error1) {
if (error1.code !== 'MODULE_NOT_FOUND') {
throw error1;
}
try {
module.exports = require("../../build/Debug/tree_sitter_vhdl_binding");
} catch (error2) {
if (error2.code !== 'MODULE_NOT_FOUND') {
throw error2;
}
throw error1
}
}
try {
module.exports.nodeTypeInfo = require("../../src/node-types.json");
} catch (_) {}

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fn main() {
let src_dir = std::path::Path::new("src");
let mut c_config = cc::Build::new();
c_config.include(&src_dir);
c_config
.flag_if_supported("-Wno-unused-parameter")
.flag_if_supported("-Wno-unused-but-set-variable")
.flag_if_supported("-Wno-trigraphs");
let parser_path = src_dir.join("parser.c");
c_config.file(&parser_path);
// If your language uses an external scanner written in C,
// then include this block of code:
/*
let scanner_path = src_dir.join("scanner.c");
c_config.file(&scanner_path);
println!("cargo:rerun-if-changed={}", scanner_path.to_str().unwrap());
*/
c_config.compile("parser");
println!("cargo:rerun-if-changed={}", parser_path.to_str().unwrap());
// If your language uses an external scanner written in C++,
// then include this block of code:
/*
let mut cpp_config = cc::Build::new();
cpp_config.cpp(true);
cpp_config.include(&src_dir);
cpp_config
.flag_if_supported("-Wno-unused-parameter")
.flag_if_supported("-Wno-unused-but-set-variable");
let scanner_path = src_dir.join("scanner.cc");
cpp_config.file(&scanner_path);
cpp_config.compile("scanner");
println!("cargo:rerun-if-changed={}", scanner_path.to_str().unwrap());
*/
}

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//! This crate provides vhdl language support for the [tree-sitter][] parsing library.
//!
//! Typically, you will use the [language][language func] function to add this language to a
//! tree-sitter [Parser][], and then use the parser to parse some code:
//!
//! ```
//! let code = "";
//! let mut parser = tree_sitter::Parser::new();
//! parser.set_language(tree_sitter_vhdl::language()).expect("Error loading vhdl grammar");
//! let tree = parser.parse(code, None).unwrap();
//! ```
//!
//! [Language]: https://docs.rs/tree-sitter/*/tree_sitter/struct.Language.html
//! [language func]: fn.language.html
//! [Parser]: https://docs.rs/tree-sitter/*/tree_sitter/struct.Parser.html
//! [tree-sitter]: https://tree-sitter.github.io/
use tree_sitter::Language;
extern "C" {
fn tree_sitter_vhdl() -> Language;
}
/// Get the tree-sitter [Language][] for this grammar.
///
/// [Language]: https://docs.rs/tree-sitter/*/tree_sitter/struct.Language.html
pub fn language() -> Language {
unsafe { tree_sitter_vhdl() }
}
/// The content of the [`node-types.json`][] file for this grammar.
///
/// [`node-types.json`]: https://tree-sitter.github.io/tree-sitter/using-parsers#static-node-types
pub const NODE_TYPES: &'static str = include_str!("../../src/node-types.json");
// Uncomment these to include any queries that this grammar contains
// pub const HIGHLIGHTS_QUERY: &'static str = include_str!("../../queries/highlights.scm");
// pub const INJECTIONS_QUERY: &'static str = include_str!("../../queries/injections.scm");
// pub const LOCALS_QUERY: &'static str = include_str!("../../queries/locals.scm");
// pub const TAGS_QUERY: &'static str = include_str!("../../queries/tags.scm");
#[cfg(test)]
mod tests {
#[test]
fn test_can_load_grammar() {
let mut parser = tree_sitter::Parser::new();
parser
.set_language(super::language())
.expect("Error loading vhdl language");
}
}

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{
"name": "tree-sitter-vhdl",
"version": "0.1.1",
"description": "VHDL grammar for tree-sitter",
"main": "bindings/node",
"scripts": {
"test": "tree-sitter test"
},
"repository": {
"type": "git",
"url": "git+https://github.com/alemuller/tree-sitter-vhdl.git"
},
"keywords": [
"parser",
"lexer",
"vhdl",
"vhdl-08",
"psl"
],
"author": "Alexandre Muller",
"license": "MIT",
"bugs": {
"url": "https://github.com/alemuller/tree-sitter-vhdl/issues"
},
"homepage": "https://github.com/alemuller/tree-sitter-vhdl#readme",
"dependencies": {
"nan": "^2.14.1"
},
"devDependencies": {
"tree-sitter-cli": "^0.20.0"
},
"tree-sitter": [
{
"scope": "source.vhd",
"file-types": [
"vhd",
"vhdl"
],
"first-line-regex": "library *;"
}
]
}

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; 3.2 Entity declaration {{{
(entity_header [
(generic_map_aspect) @error.illegal.map_aspect.generic
(port_map_aspect) @error.illegal.map_aspect.port
])
(entity_header
(port_clause)
(generic_clause) @error.order.generic_after_port)
(entity_header
(port_clause)
(port_clause) @error.repeated.clause.port)
(entity_header
(generic_clause)
(generic_clause) @error.repeated.clause.generic)
(entity_header [
(generic_clause ")" @error.missing.semicolon.after_clause .)
(port_clause ")" @error.missing.semicolon.after_clause .)
])
(entity_declaration
(declarative_part [
(variable_declaration)
(component_declaration)
(configuration_specification)
] @error.illegal.declaration))
(entity_declaration
(concurrent_statement_part [
(block_statement)
(component_instantiation_statement)
(simple_concurrent_signal_assignment)
(conditional_concurrent_signal_assignment)
(selected_concurrent_signal_assignment)
(for_generate_statement)
(if_generate_statement)
(case_generate_statement)
(PSL_Property_Declaration)
(PSL_Sequence_Declaration)
(PSL_Clock_Declaration)
] @error.illegal.statement))
;; tree-sitter-cli
;; NOTE: Only simple cases
(entity_declaration
(concurrent_statement_part
(process_statement
(sequence_of_statements [
(simple_waveform_assignment)
(simple_force_assignment)
(simple_release_assignment)
] @error.illegal.assignment.in_passive_process))
))
;; nvim-tree-sitter
((simple_waveform_assignment)
(#has-ancestor?
@error.illegal.assignment.in_passive_process
entity_declaration))
;; nvim-tree-sitter
((simple_force_assignment)
(#has-ancestor?
@error.illegal.assignment.in_passive_process
entity_declaration))
;; nvim-tree-sitter
((simple_release_assignment)
(#has-ancestor?
@error.illegal.assignment.in_passive_process
entity_declaration))
((entity_declaration
name: (_) @_h
at_end: (_) @error.misspeling.name @_t)
(#not-eq? @_h @_t))
; }}}
; 3.3 Architecture bodies {{{
(architecture_body
(declarative_part
(variable_declaration) @error.illegal.declaration))
((architecture_body
name: (_) @_h
at_end: (_) @error.misspeling.name @_t)
(#not-eq? @_h @_t))
; }}}
; 4.2 Subprogram declaration {{{
(procedure_declaration
["pure" "impure"] @error.unexpected.purity)
(procedure_declaration
designator: (operator_symbol) @error.illegal.designator.operator_symbol)
(procedure_declaration
(return) @error.unexpected.return)
;;
(function_declaration
designator: (_) . (function_parameter_clause)? . ";" @error.missing.return)
;;
(subprogram_header [
(port_clause) @error.illegal.clause.port
(port_map_aspect) @error.illegal.map_aspect.port
])
(subprogram_header
(generic_clause)
(generic_clause) @error.repeated.clause.generic)
(subprogram_header
(generic_map_aspect)
(generic_map_aspect) @error.repeated.map_aspect.generic)
; FIXME
; Negation rule not supported yet (tree-sitter version v0.19.4)
;(subprogram_header
; . !(generic_clause)*
; . (generic_map_aspect ["generic" "map"] @error.missing.clause.generic)
; . !(generic_clause)*)
; WORKARROUND
; Only single common case
(subprogram_header
. (generic_map_aspect) @error.missing.clause.generic
. )
(subprogram_header
(generic_map_aspect)
(generic_clause) @error.order.clause_after_map_aspect)
(subprogram_header [
(generic_clause (semicolon) @error.unexpected.semicolon.after_clause .)
(generic_map_aspect (semicolon) @error.unexpected.semicolon.after_map_aspect .)
])
; }}}
; 4.2 Subprogram bodies {{{
(procedure_body
["pure" "impure"] @error.unexpected.purity)
(procedure_body
designator: (operator_symbol) @error.illegal.designator.operator_symbol)
(procedure_body
at_end: (operator_symbol) @error.illegal.designator.operator_symbol)
(procedure_body
(return) @error.unexpected.return)
(procedure_body
(declarative_part [
(incomplete_type_declaration)
(signal_declaration)
(component_declaration)
(configuration_specification)
(disconnection_specification)
(PSL_Assert_Directive)
(PSL_Assume_Directive)
(PSL_Assume_Guarantee_Directive)
(PSL_Restrict_Directive)
(PSL_Restrict_Guarantee_Directive)
(PSL_Cover_Directive)
(PSL_Fairness_Directive)
(PSL_Strong_Fairness_Directive)
(PSL_Property_Declaration)
(PSL_Sequence_Declaration)
(PSL_Clock_Declaration)
] @error.illegal.declaration))
(procedure_body
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared)))
(procedure_body
"procedure"
at_end: "function" @error.misspeling.subprogram_kind)
((procedure_body
designator: (_) @_h
at_end: (_) @error.misspeling.designator @_t)
(#not-eq? @_h @_t))
;;
(function_body
designator: (_) . (function_parameter_clause)? . "is" @error.missing.return)
(function_body
at_end: ["pure" "impure"] @error.unexpected.purity.at_end)
(function_body
(declarative_part [
(signal_declaration)
(component_declaration)
(configuration_specification)
(disconnection_specification)
(PSL_Assert_Directive)
(PSL_Assume_Directive)
(PSL_Assume_Guarantee_Directive)
(PSL_Restrict_Directive)
(PSL_Restrict_Guarantee_Directive)
(PSL_Cover_Directive)
(PSL_Fairness_Directive)
(PSL_Strong_Fairness_Directive)
(PSL_Property_Declaration)
(PSL_Sequence_Declaration)
(PSL_Clock_Declaration)
] @error.illegal.declaration))
(function_body
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared)))
(function_body
"function"
at_end: "procedure" @error.misspeling.subprogram_kind)
((function_body
designator: (_) @_h
at_end: (_) @error.misspeling.designator @_t)
(#not-eq? @_h @_t))
; }}}
; 4.3 Subprogram instantiation {{{
(procedure_instantiation_declaration
["pure" "impure"] @error.unexpected.purity)
(procedure_instantiation_declaration
designator: (operator_symbol) @error.illegal.designator.operator_symbol)
(procedure_instantiation_declaration
(signature (return) @error.unexpected.return))
;;
(function_instantiation_declaration
(signature (type_mark) ("," (type_mark))* . "]" @error.missing.return))
;;
(subprogram_map_aspect [
(generic_clause) @error.illegal.clause.generic
(port_clause) @error.illegal.clause.port
(port_map_aspect) @error.illegal.map_aspect.port
])
(subprogram_map_aspect
(generic_map_aspect)
(generic_map_aspect) @error.repeated.map_aspect.generic)
(subprogram_map_aspect
(generic_map_aspect (semicolon) @error.unexpected.semicolon.after_map_aspect .))
; }}}
; 4.2.2.1 Formal parameter list {{{
(procedure_parameter_clause [
(signal_interface_declaration (mode ["buffer" "linkage"]) @error.illegal.mode)
(variable_interface_declaration (mode ["buffer" "linkage"]) @error.illegal.mode)
(signal_interface_declaration (default_expression) @error.illegal.default_expression)
(type_interface_declaration) @error.illegal.interface.type
(procedure_interface_declaration) @error.illegal.interface.procedure
(function_interface_declaration) @error.illegal.interface.function
(package_interface_declaration) @error.illegal.interface.package
])
(function_parameter_clause [
(signal_interface_declaration (mode ["out" "inout" "buffer" "linkage"]) @error.illegal.mode)
(signal_interface_declaration (default_expression) @error.illegal.default_expression)
(variable_interface_declaration) @error.illegal.interface.variable
(file_interface_declaration) @error.illegal.interface.file
(type_interface_declaration) @error.illegal.interface.type
(procedure_interface_declaration) @error.illegal.interface.procedure
(function_interface_declaration) @error.illegal.interface.function
(package_interface_declaration) @error.illegal.interface.package
])
; }}}
; 4.5 Subprogram overloading {{{
((operator_symbol) @error.illegal.operator_symbol
(#not-match? @error.illegal.operator_symbol "^\"(and|or|nand|nor|xnor|s[rl]l|s[rl]a|ro[rl]|mod|rem|abs|not|\\+|\\-|&|\\?\\?|\\??[<>/]?=|\\??[<>]|\\*\\??)\"$"))
; }}}
; 4.5.3 Signatures {{{
(signature
"[" . "]" @error.missing.type_mark)
(return
"," @error.unexpected.comma)
; }}}
; 4.7 Package declarations {{{
(package_header [
(port_clause) @error.illegal.clause.port
(port_map_aspect) @error.illegal.map_aspect.port
])
(package_header
(generic_clause)
(generic_clause) @error.repeated.clause.generic)
(package_header
(generic_map_aspect)
(generic_map_aspect) @error.repeated.map_aspect.generic)
; FIXME
; Negation rule not supported yet (tree-sitter version v0.19.4)
;(package_header
; . !(generic_clause)*
; . (generic_map_aspect) @error.missing.clause.generic
; . !(generic_clause)*)
; WORKARROUND
; Only common case
(package_header
. (generic_map_aspect) @error.missing.clause.generic
. )
(package_header
(generic_map_aspect)
(generic_clause) @error.order.clause_after_map_aspect)
(package_header [
(generic_clause ")" @error.missing.semicolon.after_clause .)
(generic_map_aspect ")" @error.missing.semicolon.after_map_aspect .)
])
(package_declaration
(declarative_part [
(procedure_body)
(function_body)
(configuration_specification)
] @error.illegal.declaration))
(package_declaration
(declarative_part
(full_type_declaration
(protected_type_body) @error.illegal.declaration)))
(procedure_body
(declarative_part
(package_declaration
(declarative_part [
(signal_declaration)
(disconnection_specification)
(PSL_Property_Declaration)
(PSL_Sequence_Declaration)
(PSL_Clock_Declaration)
] @error.illegal.declaration))))
(procedure_body
(declarative_part
(package_declaration
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared)))))
(function_body
(declarative_part
(package_declaration
(declarative_part [
(signal_declaration)
(disconnection_specification)
(PSL_Property_Declaration)
(PSL_Sequence_Declaration)
(PSL_Clock_Declaration)
] @error.illegal.declaration))))
(function_body
(declarative_part
(package_declaration
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared)))))
(process_statement
(declarative_part
(package_declaration
(declarative_part [
(signal_declaration)
(disconnection_specification)
(PSL_Property_Declaration)
(PSL_Sequence_Declaration)
(PSL_Clock_Declaration)
] @error.illegal.declaration))))
(process_statement
(declarative_part
(package_declaration
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared)))))
(full_type_declaration
(protected_type_body
(declarative_part
(package_declaration
(declarative_part [
(signal_declaration)
(disconnection_specification)
(PSL_Property_Declaration)
(PSL_Sequence_Declaration)
(PSL_Clock_Declaration)
] @error.illegal.declaration)))))
(full_type_declaration
(protected_type_body
(declarative_part
(package_declaration
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared))))))
((package_declaration
name: (_) @_h
at_end: (_) @error.misspeling.name @_t)
(#not-eq? @_h @_t))
; }}}
; 4.8 Package bodies {{{
(package_body
(declarative_part [
(signal_declaration)
(component_declaration)
(configuration_specification)
(disconnection_specification)
(PSL_Assert_Directive)
(PSL_Assume_Directive)
(PSL_Assume_Guarantee_Directive)
(PSL_Restrict_Directive)
(PSL_Restrict_Guarantee_Directive)
(PSL_Cover_Directive)
(PSL_Fairness_Directive)
(PSL_Strong_Fairness_Directive)
(PSL_Property_Declaration)
(PSL_Sequence_Declaration)
(PSL_Clock_Declaration)
] @error.illegal.declaration))
(procedure_body
(declarative_part
(package_body
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared)))))
(function_body
(declarative_part
(package_body
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared)))))
(process_statement
(declarative_part
(package_body
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared)))))
(full_type_declaration
(protected_type_body
(declarative_part
(package_body
(declarative_part
(shared_variable_declaration "shared" @error.unexpected.shared))))))
((package_body
package: (_) @_h
at_end: (_) @error.misspeling.name @_t)
(#not-eq? @_h @_t))
; }}}
; 4.9 Package instantiation declarations {{{
(package_map_aspect [
(generic_clause) @error.illegal.clause.generic
(port_clause) @error.illegal.clause.port
(port_map_aspect) @error.illegal.map_aspect.port
])
(package_map_aspect
(generic_map_aspect)
(generic_map_aspect) @error.repeated.map_aspect.generic)
(package_map_aspect
(generic_map_aspect (semicolon) @error.unexpected.semicolon.after_map_aspect .))
; }}}
; 5.2 Scalar types {{{
(ascending_range
low: (simple_expression (integer_decimal))
high: (simple_expression (real_decimal))) @error.illegal.range
(ascending_range
low: (simple_expression (real_decimal))
high: (simple_expression (integer_decimal))) @error.illegal.range
(descending_range
high: (simple_expression (integer_decimal))
low: (simple_expression (real_decimal))) @error.illegal.range
(descending_range
high: (simple_expression (real_decimal))
low: (simple_expression (integer_decimal))) @error.illegal.range
; }}}
; 5.2.2 Enumeration types {{{
((enumeration_type_definition
literal: (_) @_a
literal: (_) @error.repeated.enumerator @_b)
(#eq? @_a @_b))
; }}}
; 5.2.4 Physical types {{{
((physical_type_definition
(primary_unit_declaration
name: (_) @_p)
(secondary_unit_declaration
name: (_) @error.repeated.unit @_s))
(#eq? @_p @_s))
((physical_type_definition
(secondary_unit_declaration
name: (_) @_a)
(secondary_unit_declaration
name: (_) @error.repeated.unit @_b))
(#eq? @_a @_b))
(secondary_unit_declaration
(physical_literal [ (real_decimal) (based_real) ] @error.illegal.floating_point))
((full_type_declaration
name: (_) @_h
(physical_type_definition
at_end: (_) @error.misspeling.name @_t))
(#not-eq? @_h @_t))
; }}}
; 5.3.2 Array types {{{
(index_constraint
(subtype_indication
(resolution_function) @error.unexpected.resolution_function))
(parameter_specification
(subtype_indication
(resolution_function) @error.unexpected.resolution_function))
(full_type_declaration
name: (_) @_t
(constrained_array_definition
(subtype_indication
(type_mark (_) @error.repeated.type @_e)))
(#eq? @_t @_e))
(full_type_declaration
name: (_) @_t
(unbounded_array_definition
(subtype_indication
(type_mark (_) @error.repeated.type @_e)))
(#eq? @_t @_e))
; }}}
; 5.3.2.3 Predefined array types {{{
; Predefine array types shall be one dimensional
(subtype_indication
(type_mark
(simple_name) @_t
(#match? @_t "^(string|(boolean|bit|integer|real|time)_vector)$"))
(array_constraint
(index_constraint
(_)
(_) @error.illegal.discrete_range)))
; String subtypes shall be indexed by positive numbers
(subtype_indication
(type_mark
(simple_name) @_t
(#eq? @_t "string"))
(array_constraint
(index_constraint
(_
(simple_expression
(integer_decimal) @error.illegal.index.zero @_l
(#eq? @_l "0"))))))
(subtype_indication
(type_mark
(simple_name) @_t
(#eq? @_t "string"))
(array_constraint
(index_constraint
(_
(simple_expression
(sign) @error.illegal.index.negative)))))
; Others predefined array types are indexed by natural numbers
(subtype_indication
(type_mark
(simple_name) @_t
(#match? @_t "^(boolean|bit|integer|real|time)_vector$"))
(array_constraint
(index_constraint
(_
(simple_expression
(sign) @error.illegal.index.negative)))))
; }}}
; 5.3.3 Record types {{{
((identifier_list
(_) @_a
(_) @error.repeated.identifier @_b)
(#eq? @_a @_b))
(record_type_definition
(element_declaration
(identifier_list (_) @_a))
(element_declaration
(identifier_list (_) @error.repeated.identifier @_b))
(#eq? @_a @_b))
((full_type_declaration
name: (_) @_h
(record_type_definition
at_end: (_) @error.misspeling.name @_t))
(#not-eq? @_h @_t))
; }}}

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -0,0 +1,224 @@
#ifndef TREE_SITTER_PARSER_H_
#define TREE_SITTER_PARSER_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdbool.h>
#include <stdint.h>
#include <stdlib.h>
#define ts_builtin_sym_error ((TSSymbol)-1)
#define ts_builtin_sym_end 0
#define TREE_SITTER_SERIALIZATION_BUFFER_SIZE 1024
typedef uint16_t TSStateId;
#ifndef TREE_SITTER_API_H_
typedef uint16_t TSSymbol;
typedef uint16_t TSFieldId;
typedef struct TSLanguage TSLanguage;
#endif
typedef struct {
TSFieldId field_id;
uint8_t child_index;
bool inherited;
} TSFieldMapEntry;
typedef struct {
uint16_t index;
uint16_t length;
} TSFieldMapSlice;
typedef struct {
bool visible;
bool named;
bool supertype;
} TSSymbolMetadata;
typedef struct TSLexer TSLexer;
struct TSLexer {
int32_t lookahead;
TSSymbol result_symbol;
void (*advance)(TSLexer *, bool);
void (*mark_end)(TSLexer *);
uint32_t (*get_column)(TSLexer *);
bool (*is_at_included_range_start)(const TSLexer *);
bool (*eof)(const TSLexer *);
};
typedef enum {
TSParseActionTypeShift,
TSParseActionTypeReduce,
TSParseActionTypeAccept,
TSParseActionTypeRecover,
} TSParseActionType;
typedef union {
struct {
uint8_t type;
TSStateId state;
bool extra;
bool repetition;
} shift;
struct {
uint8_t type;
uint8_t child_count;
TSSymbol symbol;
int16_t dynamic_precedence;
uint16_t production_id;
} reduce;
uint8_t type;
} TSParseAction;
typedef struct {
uint16_t lex_state;
uint16_t external_lex_state;
} TSLexMode;
typedef union {
TSParseAction action;
struct {
uint8_t count;
bool reusable;
} entry;
} TSParseActionEntry;
struct TSLanguage {
uint32_t version;
uint32_t symbol_count;
uint32_t alias_count;
uint32_t token_count;
uint32_t external_token_count;
uint32_t state_count;
uint32_t large_state_count;
uint32_t production_id_count;
uint32_t field_count;
uint16_t max_alias_sequence_length;
const uint16_t *parse_table;
const uint16_t *small_parse_table;
const uint32_t *small_parse_table_map;
const TSParseActionEntry *parse_actions;
const char * const *symbol_names;
const char * const *field_names;
const TSFieldMapSlice *field_map_slices;
const TSFieldMapEntry *field_map_entries;
const TSSymbolMetadata *symbol_metadata;
const TSSymbol *public_symbol_map;
const uint16_t *alias_map;
const TSSymbol *alias_sequences;
const TSLexMode *lex_modes;
bool (*lex_fn)(TSLexer *, TSStateId);
bool (*keyword_lex_fn)(TSLexer *, TSStateId);
TSSymbol keyword_capture_token;
struct {
const bool *states;
const TSSymbol *symbol_map;
void *(*create)(void);
void (*destroy)(void *);
bool (*scan)(void *, TSLexer *, const bool *symbol_whitelist);
unsigned (*serialize)(void *, char *);
void (*deserialize)(void *, const char *, unsigned);
} external_scanner;
const TSStateId *primary_state_ids;
};
/*
* Lexer Macros
*/
#define START_LEXER() \
bool result = false; \
bool skip = false; \
bool eof = false; \
int32_t lookahead; \
goto start; \
next_state: \
lexer->advance(lexer, skip); \
start: \
skip = false; \
lookahead = lexer->lookahead;
#define ADVANCE(state_value) \
{ \
state = state_value; \
goto next_state; \
}
#define SKIP(state_value) \
{ \
skip = true; \
state = state_value; \
goto next_state; \
}
#define ACCEPT_TOKEN(symbol_value) \
result = true; \
lexer->result_symbol = symbol_value; \
lexer->mark_end(lexer);
#define END_STATE() return result;
/*
* Parse Table Macros
*/
#define SMALL_STATE(id) id - LARGE_STATE_COUNT
#define STATE(id) id
#define ACTIONS(id) id
#define SHIFT(state_value) \
{{ \
.shift = { \
.type = TSParseActionTypeShift, \
.state = state_value \
} \
}}
#define SHIFT_REPEAT(state_value) \
{{ \
.shift = { \
.type = TSParseActionTypeShift, \
.state = state_value, \
.repetition = true \
} \
}}
#define SHIFT_EXTRA() \
{{ \
.shift = { \
.type = TSParseActionTypeShift, \
.extra = true \
} \
}}
#define REDUCE(symbol_val, child_count_val, ...) \
{{ \
.reduce = { \
.type = TSParseActionTypeReduce, \
.symbol = symbol_val, \
.child_count = child_count_val, \
__VA_ARGS__ \
}, \
}}
#define RECOVER() \
{{ \
.type = TSParseActionTypeRecover \
}}
#define ACCEPT_INPUT() \
{{ \
.type = TSParseActionTypeAccept \
}}
#ifdef __cplusplus
}
#endif
#endif // TREE_SITTER_PARSER_H_

@ -0,0 +1,30 @@
==============================
Minimal
==============================
architecture rtl of ent is
begin
end;
architecture rtl of ent is
begin
end architecture;
architecture rtl of ent is
begin
end architecture rtl;
---
(design_file
(design_unit
(architecture_body
name: (identifier)
entity: (simple_name)))
(design_unit
(architecture_body
name: (identifier)
entity: (simple_name)))
(design_unit
(architecture_body
name: (identifier)
entity: (simple_name)
at_end: (simple_name))))

@ -0,0 +1,289 @@
================================================================================
Conditional waveform assignment - Minimal
================================================================================
t <= w when true;
L: t <= w when true;
--------------------------------------------------------------------------------
(design_file
(conditional_concurrent_signal_assignment
target: (simple_name)
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name))))
(conditional_concurrent_signal_assignment
(label
(identifier))
target: (simple_name)
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name)))))
================================================================================
Conditional waveform assignment - Delay mechanism
================================================================================
t <= transport w when true;
t <= inertial w when true;
t <= reject 10 ns inertial w when true;
--------------------------------------------------------------------------------
(design_file
(conditional_concurrent_signal_assignment
target: (simple_name)
(delay_mechanism
(transport))
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name))))
(conditional_concurrent_signal_assignment
target: (simple_name)
(delay_mechanism
(inertial))
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name))))
(conditional_concurrent_signal_assignment
target: (simple_name)
(delay_mechanism
(inertial
reject: (time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name)))))
================================================================================
Conditional waveforms I
================================================================================
t <= w1 when true else
w2 when false;
--------------------------------------------------------------------------------
(design_file
(conditional_concurrent_signal_assignment
target: (simple_name)
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name))
(alternative_conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name))))))
================================================================================
Conditional waveforms II
================================================================================
t <= w1 when cond1 else
w2 when cond2 else
w3 when cond3 else
w4;
--------------------------------------------------------------------------------
(design_file
(conditional_concurrent_signal_assignment
target: (simple_name)
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name))
(alternative_conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name)))
(alternative_conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name)))
(alternative_conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))))))
================================================================================
Conditional waveforms III
================================================================================
t <= w1 after 10 ns when cond1 else w2;
--------------------------------------------------------------------------------
(design_file
(conditional_concurrent_signal_assignment
target: (simple_name)
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
(conditional_expression
(simple_name))
(alternative_conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))))))
================================================================================
Conditional force assignment
================================================================================
t <= force w when true;
t <= force in w when true;
t <= force out w when true;
--------------------------------------------------------------------------------
(design_file
(conditional_force_assignment
target: (simple_name)
(conditional_expressions
(expression
(simple_name))
(conditional_expression
(simple_name))))
(conditional_force_assignment
target: (simple_name)
(force_mode)
(conditional_expressions
(expression
(simple_name))
(conditional_expression
(simple_name))))
(conditional_force_assignment
target: (simple_name)
(force_mode)
(conditional_expressions
(expression
(simple_name))
(conditional_expression
(simple_name)))))
================================================================================
LRM
================================================================================
S <= unaffected when Input_pin = S'Driving_Value else
Input_pin after Buffer_Delay;
--------------------------------------------------------------------------------
(design_file
(conditional_concurrent_signal_assignment
target: (simple_name)
(conditional_waveforms
(waveforms
(unaffected))
(conditional_expression
(relation
(simple_name)
(attribute_name
prefix: (simple_name)
designator: (predefined_designator))))
(alternative_conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))
(time_expression
(simple_name))))))))
================================================================================
Guarded assignment
================================================================================
t <= guarded w when cond;
--------------------------------------------------------------------------------
(design_file
(conditional_concurrent_signal_assignment
target: (simple_name)
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name)))))
================================================================================
Guarded assignment - Delay mechanism
================================================================================
t <= guarded transport w when cond;
t <= guarded inertial w when cond;
t <= guarded reject 10 ns inertial w when cond;
--------------------------------------------------------------------------------
(design_file
(conditional_concurrent_signal_assignment
target: (simple_name)
(delay_mechanism
(transport))
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name))))
(conditional_concurrent_signal_assignment
target: (simple_name)
(delay_mechanism
(inertial))
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name))))
(conditional_concurrent_signal_assignment
target: (simple_name)
(delay_mechanism
(inertial
reject: (time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
(conditional_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(conditional_expression
(simple_name)))))

@ -0,0 +1,355 @@
================================================================================
Selected waveform assignment - Minimal
================================================================================
with expr select
t <= w when true;
L1:
with expr select
t <= w when true;
with expr select?
t <= w when true;
L2:
with expr select?
t <= w when true;
--------------------------------------------------------------------------------
(design_file
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name)))))
(selected_concurrent_signal_assignment
(label
(identifier))
(expression
(simple_name))
target: (simple_name)
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name)))))
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name)))))
(selected_concurrent_signal_assignment
(label
(identifier))
(expression
(simple_name))
target: (simple_name)
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name))))))
================================================================================
Selected waveform assignment - Delay mechanism
================================================================================
with expr select
t <= transport w when true;
with expr select
t <= inertial w when true;
with expr select
t <= reject 10 ns inertial w when true;
--------------------------------------------------------------------------------
(design_file
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(delay_mechanism
(transport))
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name)))))
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(delay_mechanism
(inertial))
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name)))))
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(delay_mechanism
(inertial
reject: (time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name))))))
================================================================================
Selected waveforms I
================================================================================
with expr select
t <= w1 when true,
w2 when false;
--------------------------------------------------------------------------------
(design_file
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name)))
(alternative_selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name)))))))
================================================================================
Selected waveforms II
================================================================================
with expr select
t <= w1 when cond1 | cond2,
w3 when others;
--------------------------------------------------------------------------------
(design_file
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name))
(simple_expression
(simple_name)))
(alternative_selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(others))))))
================================================================================
Selected waveforms III
================================================================================
with expr select
t <= w1 after 10 ns when cond1,
w2 when others;
--------------------------------------------------------------------------------
(design_file
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
(choices
(simple_expression
(simple_name)))
(alternative_selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(others))))))
================================================================================
Selected force assignment
================================================================================
with expr select
t <= force w when true;
with expr select
t <= force in w when true;
with expr select
t <= force out w when true;
--------------------------------------------------------------------------------
(design_file
(selected_force_assignment
(expression
(simple_name))
target: (simple_name)
(selected_expressions
(expression
(simple_name))
(choices
(simple_expression
(simple_name)))))
(selected_force_assignment
(expression
(simple_name))
target: (simple_name)
(force_mode)
(selected_expressions
(expression
(simple_name))
(choices
(simple_expression
(simple_name)))))
(selected_force_assignment
(expression
(simple_name))
target: (simple_name)
(force_mode)
(selected_expressions
(expression
(simple_name))
(choices
(simple_expression
(simple_name))))))
================================================================================
Guarded assignment
================================================================================
with expr select
t <= guarded w when cond;
--------------------------------------------------------------------------------
(design_file
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name))))))
================================================================================
Guarded assignment - Delay mechanism
================================================================================
with expr select
t <= guarded transport w when cond;
with expr select
t <= guarded inertial w when cond;
with expr select
t <= guarded reject 10 ns inertial w when cond;
--------------------------------------------------------------------------------
(design_file
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(delay_mechanism
(transport))
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name)))))
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(delay_mechanism
(inertial))
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name)))))
(selected_concurrent_signal_assignment
(expression
(simple_name))
target: (simple_name)
(delay_mechanism
(inertial
reject: (time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
(selected_waveforms
(waveforms
(waveform_element
(expression
(simple_name))))
(choices
(simple_expression
(simple_name))))))

@ -0,0 +1,187 @@
================================================================================
Simple waveform assignment - Minimal
================================================================================
t <= w;
L: t <= w;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_name)))))
(simple_concurrent_signal_assignment
(label
(identifier))
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_name))))))
================================================================================
Simple waveform assignment - Delay mechanism
================================================================================
t <= transport w;
t <= inertial w;
t <= reject 10 ns inertial w;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(delay_mechanism
(transport))
(waveforms
(waveform_element
(expression
(simple_name)))))
(simple_concurrent_signal_assignment
target: (simple_name)
(delay_mechanism
(inertial))
(waveforms
(waveform_element
(expression
(simple_name)))))
(simple_concurrent_signal_assignment
target: (simple_name)
(delay_mechanism
(inertial
reject: (time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
(waveforms
(waveform_element
(expression
(simple_name))))))
================================================================================
Waveform element
================================================================================
t <= val;
t <= val after 42 ns;
t <= null after 42 ns;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_name)))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_name))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(null))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))))
================================================================================
Waveforms
================================================================================
t <= unaffected;
t <= val1 after 10 ns,
val2 after 20 ns,
null;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(unaffected)))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_name))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name))))
(waveform_element
(expression
(simple_name))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name))))
(waveform_element
(expression
(null))))))
================================================================================
Simple force assignment
================================================================================
t <= force expr;
t <= force in expr;
t <= force out expr;
--------------------------------------------------------------------------------
(design_file
(simple_force_assignment
target: (simple_name)
(expression
(simple_name)))
(simple_force_assignment
target: (simple_name)
(force_mode)
(expression
(simple_name)))
(simple_force_assignment
target: (simple_name)
(force_mode)
(expression
(simple_name))))
================================================================================
Simple release assignment
================================================================================
t <= release;
t <= release in;
t <= release out;
--------------------------------------------------------------------------------
(design_file
(simple_release_assignment
target: (simple_name))
(simple_release_assignment
target: (simple_name)
(force_mode))
(simple_release_assignment
target: (simple_name)
(force_mode)))
================================================================================
Guarded assignment
================================================================================
t <= guarded w;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_name))))))

@ -0,0 +1,57 @@
==============================
Minimal
==============================
assert a;
A1: assert a;
---
(design_file
(assertion_statement
(conditional_expression
(simple_name)))
(assertion_statement
(label
(identifier))
(conditional_expression
(simple_name))))
==============================
Report
==============================
assert a report "str";
---
(design_file
(assertion_statement
(conditional_expression
(simple_name))
(string_expression
(string_literal))))
==============================
Severity
==============================
assert a severity note;
---
(design_file
(assertion_statement
(conditional_expression
(simple_name))
(severity_expression
(simple_name))))
==============================
Report and severity
==============================
assert a report K_MSG severity failure;
---
(design_file
(assertion_statement
(conditional_expression
(simple_name))
(string_expression
(simple_name))
(severity_expression
(simple_name))))

@ -0,0 +1,176 @@
==============================
Minimal
==============================
L1: block
begin
end block;
B2: block is
begin
end block B2;
----
(design_file
(block_statement
(label (identifier)))
(block_statement
(label (identifier))
at_end: (simple_name)))
==============================
Guard condition
==============================
L1: block (cond) is
begin
end block;
---
(design_file
(block_statement
(label
(identifier))
guard: (conditional_expression
(simple_name))))
==============================
Block header - Generic clause
==============================
L1: block is
generic (a:t);
begin
end block;
---
(design_file
(block_statement
(label
(identifier))
(block_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))))
==================================
Block header - Generic map aspect
==================================
L1: block is
generic (a:t);
generic map (b);
begin
end block;
---
(design_file
(block_statement
(label
(identifier))
(block_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon))
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))
(semicolon)))))
==============================
Block header - Port clause
==============================
L1: block is
port (a:t);
begin
end block;
---
(design_file
(block_statement
(label
(identifier))
(block_header
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))))
==============================
Block header - Port map aspect
==============================
L1: block is
port (a:t);
port map (b);
begin
end block;
---
(design_file
(block_statement
(label
(identifier))
(block_header
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon))
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))
(semicolon)))))
==============================
Declarative part
==============================
L1: block is
alias a is s;
begin
end block;
---
(design_file
(block_statement
(label
(identifier))
(declarative_part
(alias_declaration
designator: (identifier)
denotator: (simple_name)))))
==============================
Sequential part
==============================
L1: block is
begin
PL: p;
end block;
---
(design_file
(block_statement
(label
(identifier))
(concurrent_statement_part
(procedure_call_statement
(label
(identifier))
procedure: (simple_name)))))

@ -0,0 +1,438 @@
================================================================================
Minimal (ambigous)
================================================================================
L1: unit;
--------------------------------------------------------------------------------
(design_file
(procedure_call_statement
(label
(identifier))
procedure: (simple_name)))
================================================================================
Minimal (ambigous) - II
================================================================================
L1: pkg.unit;
--------------------------------------------------------------------------------
(design_file
(procedure_call_statement
(label
(identifier))
procedure: (selected_name
prefix: (simple_name)
suffix: (simple_name))))
================================================================================
Instantiation unit - Component
================================================================================
L1: component unit;
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))))
================================================================================
Instantiation unit - Entity I
================================================================================
L1: entity lib.e;
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(entity_instantiation
entity: (selected_name
prefix: (simple_name)
suffix: (simple_name)))))
================================================================================
Instantiation unit - Entity II
================================================================================
L1: entity lib.e(rtl);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(entity_instantiation
entity: (selected_name
prefix: (simple_name)
suffix: (simple_name))
architecture: (simple_name))))
================================================================================
Instantiation unit - Configuration
================================================================================
L1: configuration lib.cfg;
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(configuration_instantiation
configuration: (selected_name
prefix: (simple_name)
suffix: (simple_name)))))
================================================================================
Generic map aspect - Simple name
================================================================================
L1: unit
generic map (a,b,c);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name))))))))
================================================================================
Generic map aspect - Expanded name
================================================================================
L1: pkg.unit
generic map (a,b,c);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (selected_name
prefix: (simple_name)
suffix: (simple_name)))
(component_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name))))))))
================================================================================
Port map aspect - Simple name
================================================================================
L1: unit
port map (a,b,c);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name))))))))
================================================================================
Port map aspect - Expanded name
================================================================================
L1: pkg.unit
port map (a,b,c);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (selected_name
prefix: (simple_name)
suffix: (simple_name)))
(component_map_aspect
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name))))))))
================================================================================
Generic and port map aspect - Simple name
================================================================================
L1: unit
generic map (a,b,c)
port map (open,a);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name)))))
(port_map_aspect
(association_list
(positional_association_element
actual_part: (open))
(positional_association_element
actual_part: (expression
(simple_name))))))))
================================================================================
Generic and port map aspect - Expanded name
================================================================================
L1: pkg.unit
generic map (a,b,c)
port map (open,a);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (selected_name
prefix: (simple_name)
suffix: (simple_name)))
(component_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name)))))
(port_map_aspect
(association_list
(positional_association_element
actual_part: (open))
(positional_association_element
actual_part: (expression
(simple_name))))))))
================================================================================
Type declaration
================================================================================
L1: unit
generic map (integer range 0 to 7);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (subtype_indication
(type_mark
(simple_name))
(range_constraint
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))))))))
================================================================================
Selected name on port map aspect
================================================================================
L1: unit
port map (a.b => c);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(port_map_aspect
(association_list
(named_association_element
formal_part: (selected_name
prefix: (simple_name)
suffix: (simple_name))
actual_part: (expression
(simple_name))))))))
================================================================================
LINT: Component instantiation - Semicolon
================================================================================
l : c
generic map (k); -- here
port map (s);
--------------------------------------------------------------------------------
(design_file
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))
(semicolon))
(comment)
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))
================================================================================
LINT: Component instantiation - Headers
================================================================================
-- Illegal
l : c
generic (k:t)
port (s:t);
-- Duplicated
l : c
generic map (s)
generic map (s);
-- Duplicated
l : c
port map (s)
port map (s);
-- Wrong order
l : c
port map (s)
generic map (s);
--------------------------------------------------------------------------------
(design_file
(comment)
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))))
(comment)
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))))
(comment)
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))))
(comment)
(component_instantiation_statement
(label
(identifier))
(component_instantiation
component: (simple_name))
(component_map_aspect
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))

@ -0,0 +1,567 @@
====================================
For generate - Minimal
====================================
G1:
for i in r
generate
end generate;
G1:
for i in r
generate
end generate G1;
---
(design_file
(for_generate_statement
(label
(identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark
(simple_name)))))
(for_generate_statement
(label
(identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark
(simple_name))))
at_end: (simple_name)))
====================================
For generate - Body
====================================
G2:
for i in r
generate
begin
end generate;
G3:
for i in r
generate
end;
end generate;
G4:
for i in r
generate
begin
end;
end generate;
---
(design_file
(for_generate_statement
(label (identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark (simple_name))))
(generate_statement_body))
(for_generate_statement
(label (identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark (simple_name))))
(generate_statement_body))
(for_generate_statement
(label (identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark (simple_name))))
(generate_statement_body)))
==================================================
Generate statement body - Block declarative part I
==================================================
G1:
for i in r
generate
subtype t is t2;
begin
end generate;
G2:
for i in r
generate
subtype t is t2;
begin
end;
end generate;
---
(design_file
(for_generate_statement
(label
(identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark
(simple_name))))
(generate_statement_body
(declarative_part
(subtype_declaration
name: (identifier)
(subtype_indication
(type_mark
(simple_name)))))))
(for_generate_statement
(label
(identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark
(simple_name))))
(generate_statement_body
(declarative_part
(subtype_declaration
name: (identifier)
(subtype_indication
(type_mark
(simple_name))))))))
==================================================
Generate statement body - Concurrent statement I
==================================================
G1:
for i in r
generate
end;
end generate;
G2:
for i in r
generate
begin
B1: block
begin
end block;
end generate;
G3:
for i in r
generate
begin
B1: block
begin
end block;
end;
end generate;
---
(design_file
(for_generate_statement
(label (identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark (simple_name))))
(generate_statement_body))
(for_generate_statement
(label (identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark (simple_name))))
(generate_statement_body
(block_statement
(label (identifier)))))
(for_generate_statement
(label (identifier))
(parameter_specification
name: (identifier)
(subtype_indication
(type_mark (simple_name))))
(generate_statement_body
(block_statement
(label (identifier))))))
====================================
If generate - Minimal
====================================
G1:
if c generate
end generate;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name)))))
====================================
If generate - Elsif I
====================================
G1:
if c1 generate
elsif c2 generate
end generate;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name)))
(elsif_generate
(conditional_expression
(simple_name)))))
====================================
If generate - Elsif II
====================================
G1:
if c1 generate
elsif c2 generate
elsif c2 generate
end generate;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name)))
(elsif_generate
(conditional_expression
(simple_name)))
(elsif_generate
(conditional_expression
(simple_name)))))
====================================
If generate - Else
====================================
G1:
if c generate
else generate
end generate;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name)))
(else_generate)))
====================================
If generate - All alternatives
====================================
G1:
if c1 generate
elsif c2 generate
else generate
end generate;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name)))
(elsif_generate
(conditional_expression
(simple_name)))
(else_generate)))
====================================
If generate - Generate body - If
====================================
G_BEGIN:
if c generate
begin
end generate;
G_END:
if c generate
end;
end generate;
G_BOTH:
if c generate
begin
end;
end generate;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name))
(generate_statement_body)))
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name))
(generate_statement_body)))
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name))
(generate_statement_body))))
====================================
If generate - Generate body - Elsif
====================================
G1:
if c generate
elsif x generate
begin
elsif x generate
end;
elsif x generate
begin
end;
end generate;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name)))
(elsif_generate
(conditional_expression
(simple_name))
(generate_statement_body))
(elsif_generate
(conditional_expression
(simple_name))
(generate_statement_body))
(elsif_generate
(conditional_expression
(simple_name))
(generate_statement_body))))
====================================
If generate - Else
====================================
G_BEGIN:
if c generate
else generate
begin
end generate;
G_END:
if c generate
else generate
end;
end generate;
G_BOTH:
if c generate
else generate
begin
end;
end generate;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name)))
(else_generate
(generate_statement_body)))
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name)))
(else_generate
(generate_statement_body)))
(if_generate_statement
(label
(identifier))
(if_generate
(conditional_expression
(simple_name)))
(else_generate
(generate_statement_body))))
====================================
If generate - Labels
====================================
G1:
if A1: c generate
elsif A2: c generate
else A3: generate
end generate G1;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(label
(identifier))
(conditional_expression
(simple_name)))
(elsif_generate
(label
(identifier))
(conditional_expression
(simple_name)))
(else_generate
(label
(identifier)))
at_end: (simple_name)))
====================================
If generate - Generate body label
====================================
G1:
if A1: c generate
elsif A2: c generate
begin
end A2;
else A3: generate
end A3;
end generate G1;
---
(design_file
(if_generate_statement
(label
(identifier))
(if_generate
(label
(identifier))
(conditional_expression
(simple_name)))
(elsif_generate
(label
(identifier))
(conditional_expression
(simple_name))
(generate_statement_body
at_end: (simple_name)))
(else_generate
(label
(identifier))
(generate_statement_body
at_end: (simple_name)))
at_end: (simple_name)))
====================================
Case generate - Minimal
====================================
G1:
case e generate
when a =>
end generate;
---
(design_file
(case_generate_statement
(label
(identifier))
(expression
(simple_name))
(case_generate_alternative
(choices
(simple_expression
(simple_name))))))
====================================
Case generate - Alternative
====================================
G1:
case e generate
when a =>
when b | c =>
when others =>
end generate;
---
(design_file
(case_generate_statement
(label
(identifier))
(expression
(simple_name))
(case_generate_alternative
(choices
(simple_expression
(simple_name))))
(case_generate_alternative
(choices
(simple_expression
(simple_name))
(simple_expression
(simple_name))))
(case_generate_alternative
(choices
(others)))))
====================================
Case generate - Generate body
====================================
G1:
case e generate
when a =>
begin
when b | c =>
end;
when others =>
begin
end;
end generate;
---
(design_file
(case_generate_statement
(label
(identifier))
(expression
(simple_name))
(case_generate_alternative
(choices
(simple_expression
(simple_name)))
(generate_statement_body))
(case_generate_alternative
(choices
(simple_expression
(simple_name))
(simple_expression
(simple_name)))
(generate_statement_body))
(case_generate_alternative
(choices
(others))
(generate_statement_body))))

@ -0,0 +1,79 @@
=============================
Minimal
=============================
process
begin
end process;
L1: process is
begin
end process L1;
---
(design_file
(process_statement)
(process_statement
(label (identifier))
at_end: (simple_name)))
=============================
Sequential statement
=============================
process
begin
wait on a;
end process;
---
(design_file
(process_statement
(sequence_of_statements
(wait_statement
(sensitivity_list
(simple_name))))))
=============================
Sensitivity list - All
=============================
process (all)
begin
end process;
---
(design_file
(process_statement
(sensitivity_list
(all))))
=============================
Sensitivity list - Signals
=============================
process (a,b)
begin
end process;
---
(design_file
(process_statement
(sensitivity_list
(simple_name)
(simple_name))))
=============================
Declarative part
=============================
process
constant k : t := g;
begin
end process;
---
(design_file
(process_statement
(declarative_part
(constant_declaration
(identifier_list (identifier))
(subtype_indication
(type_mark (simple_name)))
(default_expression
(simple_name))))))

@ -0,0 +1,77 @@
===================================
Conflict I - Function call
===================================
assert (foo (open));
---
(design_file
(assertion_statement
(conditional_expression
(parenthesized_expression
(function_call
function: (simple_name)
(association_list
(positional_association_element
actual_part: (open))))))))
===================================
Conflict I - Subtype indication constraint
===================================
assert new foobar (foo (open));
---
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(record_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(open))))))))))
===================================
Conflict II - Slice name
===================================
assert (foo (h downto l));
---
(design_file
(assertion_statement
(conditional_expression
(parenthesized_expression
(slice_name
prefix: (simple_name)
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name))))))))
===================================
Conflict II - Subtype indication constraint
===================================
assert new foobar (foo (h downto l));
---
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(record_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name))))))))))))

@ -0,0 +1,13 @@
==============
Minimal
==============
type foo is access bar;
---
(design_file
(full_type_declaration
(identifier)
(access_type_definition
(subtype_indication
(type_mark
(simple_name))))))

@ -0,0 +1,70 @@
===========================
Designator - Identifier
===========================
alias a is b;
---
(design_file
(alias_declaration
designator: (identifier)
denotator: (simple_name)))
==============================
Designator - Character literal
==============================
alias '0' is STD.STANDARD.'0' [return STD.STANDARD.BIT];
---
(design_file
(alias_declaration
designator: (character_literal)
denotator: (selected_name
prefix: (selected_name
prefix: (simple_name)
suffix: (simple_name))
suffix: (character_literal))
(signature
(return
(type_mark
(selected_name
prefix: (selected_name
prefix: (simple_name)
suffix: (simple_name))
suffix: (simple_name)))))))
==============================
Designator - Operator symbol
==============================
alias "or" is STD.STANDARD."or" [STD.STANDARD.BIT,
STD.STANDARD.BIT
return STD.STANDARD.BIT];
---
(design_file
(alias_declaration
designator: (operator_symbol)
denotator: (selected_name
prefix: (selected_name
prefix: (simple_name)
suffix: (simple_name))
suffix: (operator_symbol))
(signature
(type_mark
(selected_name
prefix: (selected_name
prefix: (simple_name)
suffix: (simple_name))
suffix: (simple_name)))
(type_mark
(selected_name
prefix: (selected_name
prefix: (simple_name)
suffix: (simple_name))
suffix: (simple_name)))
(return
(type_mark
(selected_name
prefix: (selected_name
prefix: (simple_name)
suffix: (simple_name))
suffix: (simple_name)))))))

@ -0,0 +1,30 @@
==============================
Minimal
==============================
architecture rtl of ent is
begin
end;
architecture rtl of ent is
begin
end architecture;
architecture rtl of ent is
begin
end architecture rtl;
---
(design_file
(design_unit
(architecture_body
name: (identifier)
entity: (simple_name)))
(design_unit
(architecture_body
name: (identifier)
entity: (simple_name)))
(design_unit
(architecture_body
name: (identifier)
entity: (simple_name)
at_end: (simple_name))))

@ -0,0 +1,123 @@
================================================================================
Declaration
================================================================================
attribute a : t;
--------------------------------------------------------------------------------
(design_file
(attribute_declaration
(identifier)
(type_mark
(simple_name))))
================================================================================
Specification
================================================================================
attribute attr of e : entity is expr;
--------------------------------------------------------------------------------
(design_file
(attribute_specification
(simple_name)
(entity_specification
(entity_name_list
(entity_designator
(simple_name)))
(entity_class))
(expression
(simple_name))))
================================================================================
Specification [LRM] I
================================================================================
attribute LOCATION of ADDER1 : label is (10,15);
--------------------------------------------------------------------------------
(design_file
(attribute_specification
(simple_name)
(entity_specification
(entity_name_list
(entity_designator
(simple_name)))
(entity_class))
(expression
(aggregate
(positional_element_association
(expression
(integer_decimal)))
(positional_element_association
(expression
(integer_decimal)))))))
================================================================================
Specification [LRM] II
================================================================================
attribute IMPLEMENTATION of G1: group is "74LS152";
--------------------------------------------------------------------------------
(design_file
(attribute_specification
(simple_name)
(entity_specification
(entity_name_list
(entity_designator
(simple_name)))
(entity_class))
(expression
(string_literal))))
================================================================================
Specification [LRM] III
================================================================================
attribute CAPACITANCE of all: signal is 15 pF;
--------------------------------------------------------------------------------
(design_file
(attribute_specification
name: (simple_name)
(entity_specification
(entity_name_list
(all))
(entity_class))
(expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
================================================================================
Xilinx Attribute I
================================================================================
attribute ASYNC_REG : string;
attribute ASYNC_REG of sync_regs : signal is "TRUE";
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of sync_regs : signal is true;
--------------------------------------------------------------------------------
(design_file
(attribute_declaration
(identifier)
(type_mark
(simple_name)))
(attribute_specification
(simple_name)
(entity_specification
(entity_name_list
(entity_designator
(simple_name)))
(entity_class))
(expression
(string_literal)))
(attribute_declaration
(identifier)
(type_mark
(simple_name)))
(attribute_specification
(simple_name)
(entity_specification
(entity_name_list
(entity_designator
(simple_name)))
(entity_class))
(expression
(simple_name))))

@ -0,0 +1,187 @@
=============================
Minimal
=============================
component c
end component;
component c is
end component;
component c is
end component c;
---
(design_file
(component_declaration
name: (identifier))
(component_declaration
name: (identifier))
(component_declaration
name: (identifier)
at_end: (simple_name)))
=============================
Header
=============================
component c
generic (k : t);
port (s : t);
end component;
---
(design_file
(component_declaration
name: (identifier)
(component_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon))
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))))
=============================
LINT: Missing semicolon
=============================
component c
generic (k:t) -- here
port (s:t) -- here
end component;
---
(design_file
(component_declaration
name: (identifier)
(component_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))
(comment)
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))))
(comment)))
=============================
LINT: Illegal headers
=============================
-- Illegal
component c
generic map (x);
port map (x);
end component;
-- Duplicated
component c
generic (k:t);
generic (k:t);
end component;
-- Duplicated
component c
port (s:t);
port (s:t);
end component;
-- Wrong order
component c
port (s:t);
generic (k:t);
end component;
---
(design_file
(comment)
(component_declaration
name: (identifier)
(component_header
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))
(semicolon))
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))
(semicolon))))
(comment)
(component_declaration
name: (identifier)
(component_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon))
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon))))
(comment)
(component_declaration
name: (identifier)
(component_header
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon))
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon))))
(comment)
(component_declaration
name: (identifier)
(component_header
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon))
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))))

@ -0,0 +1,151 @@
================================================================================
Unbounded array type I
================================================================================
type att_t is array (a range <>) of b;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(unbounded_array_definition
(index_subtype_definition
(type_mark
(simple_name))
(any))
element: (subtype_indication
(type_mark
(simple_name))))))
================================================================================
Unbounded array type II
================================================================================
type att_t is array (a range <>, b range <>) of c;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(unbounded_array_definition
(index_subtype_definition
(type_mark
(simple_name))
(any))
(index_subtype_definition
(type_mark
(simple_name))
(any))
element: (subtype_indication
(type_mark
(simple_name))))))
================================================================================
Constrained array type - Subtype indication
================================================================================
type att_t is array (subtype_t) of foo;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(constrained_array_definition
(index_constraint
(subtype_indication
(type_mark
(simple_name))))
element: (subtype_indication
(type_mark
(simple_name))))))
================================================================================
Constrained array type - Range
================================================================================
type att_t is array (7 downto 0) of foo;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(constrained_array_definition
(index_constraint
(descending_range
high: (simple_expression
(integer_decimal))
low: (simple_expression
(integer_decimal))))
element: (subtype_indication
(type_mark
(simple_name))))))
================================================================================
Record type I
================================================================================
type rec_t is
record
e1 : elemt_t;
end record;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(record_type_definition
(element_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))))
================================================================================
Record type II
================================================================================
type rec_t is
record
e1 : arr (st);
end record;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(record_type_definition
(element_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))
(array_constraint
(index_constraint
(subtype_indication
(type_mark
(simple_name))))))))))
================================================================================
Record type III
================================================================================
type rec_t is
record
e1 : elemt_t;
e2, e3 : elemt_t;
end record rec_t;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(record_type_definition
(element_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(element_declaration
(identifier_list
(identifier)
(identifier))
(subtype_indication
(type_mark
(simple_name))))
at_end: (simple_name))))

@ -0,0 +1,173 @@
================================================================================
Minimal
================================================================================
configuration cfg of ent is
end;
configuration cfg of ent is
end configuration;
configuration cfg of ent is
end configuration cfg;
--------------------------------------------------------------------------------
(design_file
(design_unit
(configuration_declaration
name: (identifier)
entity: (simple_name)))
(design_unit
(configuration_declaration
name: (identifier)
entity: (simple_name)))
(design_unit
(configuration_declaration
name: (identifier)
entity: (simple_name)
at_end: (simple_name))))
================================================================================
Expanded name
================================================================================
configuration cfg of lib.ent is
end;
--------------------------------------------------------------------------------
(design_file
(design_unit
(configuration_declaration
name: (identifier)
entity: (selected_name
prefix: (simple_name)
suffix: (simple_name)))))
================================================================================
Block configuration - Minimal
================================================================================
configuration cfg of ent is
for arch
end for;
end;
configuration cfg of ent is
for gen(GEN1)
end for;
end;
configuration cfg of ent is
for gen(0 to 1)
end for;
end;
configuration cfg of ent is
for gen(1+1)
end for;
end;
--------------------------------------------------------------------------------
(design_file
(design_unit
(configuration_declaration
name: (identifier)
entity: (simple_name)
(block_configuration
(block_specification
name_or_label: (simple_name)))))
(design_unit
(configuration_declaration
name: (identifier)
entity: (simple_name)
(block_configuration
(block_specification
(generate_statement_element
label: (simple_name)
specification: (simple_name))))))
(design_unit
(configuration_declaration
name: (identifier)
entity: (simple_name)
(block_configuration
(block_specification
(generate_statement_element
label: (simple_name)
specification: (ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))))))
(design_unit
(configuration_declaration
name: (identifier)
entity: (simple_name)
(block_configuration
(block_specification
(generate_statement_element
label: (simple_name)
specification: (expression
(simple_expression
(integer_decimal)
(integer_decimal)))))))))
================================================================================
LRM 3.4.1
================================================================================
library TTL, Work;
configuration V4_27_87 of Processor is
use Work.all;
for Structure_View
for A1: ALU
use configuration TTL.SN74LS181;
end for;
for M1,M2,M3: MUX
use entity Multiplex4 (Behavior);
end for;
for all: Latch
-- use defaults
end for;
end for;
end configuration V4_27_87;
--------------------------------------------------------------------------------
(design_file
(design_unit
(context_clause
(library_clause
(logical_name_list
library: (simple_name)
library: (simple_name))))
(configuration_declaration
name: (identifier)
entity: (simple_name)
(declarative_part
(use_clause
(selected_name
prefix: (simple_name)
suffix: (all))))
(block_configuration
(block_specification
name_or_label: (simple_name))
(component_configuration
(instantiation_list
(simple_name))
component: (simple_name)
(binding_indication
(configuration_instantiation
configuration: (selected_name
prefix: (simple_name)
suffix: (simple_name)))))
(component_configuration
(instantiation_list
(simple_name)
(simple_name)
(simple_name))
component: (simple_name)
(binding_indication
(entity_instantiation
entity: (simple_name)
architecture: (simple_name))))
(component_configuration
(instantiation_list
(all))
component: (simple_name)
(comment)))
at_end: (simple_name))))

@ -0,0 +1,324 @@
=============================================
Simple configuration specification
=============================================
for l : c
use open;
for l : c
use open;
end for;
---
(design_file
(configuration_specification
(instantiation_list
(simple_name))
component: (simple_name)
(binding_indication (open)))
(configuration_specification
(instantiation_list
(simple_name))
component: (simple_name)
(binding_indication (open))))
=============================================
Compound configuration specification
=============================================
for l : c
use open;
use vunit vu;
end for;
---
(design_file
(configuration_specification
(instantiation_list
(simple_name))
component: (simple_name)
(binding_indication (open))
(verification_unit_binding_indication
(verification_unit_list
(simple_name)))))
=============================================
Instantiation list
=============================================
for l1, l2 : c
use open;
for others : c
use open;
for all : c
use open;
---
(design_file
(configuration_specification
(instantiation_list
(simple_name)
(simple_name))
component: (simple_name)
(binding_indication (open)))
(configuration_specification
(instantiation_list (others))
component: (simple_name)
(binding_indication (open)))
(configuration_specification
(instantiation_list (all))
component: (simple_name)
(binding_indication (open))))
=============================================
Binding indication - Entity aspect
=============================================
for all : c
use entity e;
for all : c
use entity e(a);
for all : c
use configuration c;
for all : c
use open;
---
(design_file
(configuration_specification
(instantiation_list (all))
component: (simple_name)
(binding_indication
(entity_instantiation
entity: (simple_name))))
(configuration_specification
(instantiation_list (all))
component: (simple_name)
(binding_indication
(entity_instantiation
entity: (simple_name)
architecture: (simple_name))))
(configuration_specification
(instantiation_list (all))
component: (simple_name)
(binding_indication
(configuration_instantiation
configuration: (simple_name))))
(configuration_specification
(instantiation_list (all))
component: (simple_name)
(binding_indication (open))))
=============================================
Binding indication - Generic map aspects
=============================================
for all : c
generic map (a);
---
(design_file
(configuration_specification
(instantiation_list
(all))
component: (simple_name)
(binding_indication
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))
=============================================
Binding indication - Port map aspects
=============================================
for all : c
port map (a);
---
(design_file
(configuration_specification
(instantiation_list
(all))
component: (simple_name)
(binding_indication
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))
=============================================
Binding indication - Both map aspects
=============================================
for all : c
generic map (a)
port map (a);
---
(design_file
(configuration_specification
(instantiation_list
(all))
component: (simple_name)
(binding_indication
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))
=============================================
LINT: Binding indication (open)
=============================================
for all : c
use open
generic map (a) -- illegal
port map (a); -- illegal
---
(design_file
(configuration_specification
(instantiation_list
(all))
component: (simple_name)
(binding_indication
(open)
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))
(comment)
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))))
(comment))
=============================================
LINT: Binding indication - Semicolon
=============================================
for all : c
generic map (x); -- here
port map (x);
---
(design_file
(configuration_specification
(instantiation_list
(all))
component: (simple_name)
(binding_indication
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))
(semicolon))
(comment)
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))
=============================================
LINT: Binding indication - Header
=============================================
-- Illegal
for all : c
generic (k:t)
port (s:t);
-- Duplicated
for all : c
generic map (x)
generic map (x);
-- Duplicated
for all : c
port map (x)
port map (x);
-- Wrong order
for all : c
port map (x)
generic map (x);
---
(design_file
(comment)
(configuration_specification
(instantiation_list
(all))
component: (simple_name)
(binding_indication
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))))
(comment)
(configuration_specification
(instantiation_list
(all))
component: (simple_name)
(binding_indication
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))))
(comment)
(configuration_specification
(instantiation_list
(all))
component: (simple_name)
(binding_indication
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))))
(comment)
(configuration_specification
(instantiation_list
(all))
component: (simple_name)
(binding_indication
(port_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))

@ -0,0 +1,58 @@
================================================================================
Minimal
================================================================================
disconnect s : t after 10 ns;
--------------------------------------------------------------------------------
(design_file
(disconnection_specification
(guarded_signal_specification
(signal_list
(simple_name))
(type_mark
(simple_name)))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
================================================================================
Signal list - Multiple signals
================================================================================
disconnect all : t after 10 ns;
disconnect others : t after 10 ns;
disconnect s1, s2 : t after 10 ns;
--------------------------------------------------------------------------------
(design_file
(disconnection_specification
(guarded_signal_specification
(signal_list
(all))
(type_mark
(simple_name)))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name))))
(disconnection_specification
(guarded_signal_specification
(signal_list
(others))
(type_mark
(simple_name)))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name))))
(disconnection_specification
(guarded_signal_specification
(signal_list
(simple_name)
(simple_name))
(type_mark
(simple_name)))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))

@ -0,0 +1,31 @@
===============================
Minimal
===============================
entity e is
end;
entity e is
end entity;
entity e is
end e;
entity e is
end entity e;
---
(design_file
(design_unit
(entity_declaration
name: (identifier)))
(design_unit
(entity_declaration
name: (identifier)))
(design_unit
(entity_declaration
name: (identifier)
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
at_end: (simple_name))))

@ -0,0 +1,12 @@
====================
Minimal
====================
type FT is file of TM;
---
(design_file
(full_type_declaration
(identifier)
(file_type_definition
(type_mark
(simple_name)))))

@ -0,0 +1,102 @@
====================================
Template - Minimal
====================================
group g is (signal);
---
(design_file
(group_template_declaration
name: (identifier)
(entity_class_entry_list
(entity_class_entry
(entity_class)))))
====================================
Template - Entry list
====================================
group g is (signal, signal);
group g is (group <>);
---
(design_file
(group_template_declaration
name: (identifier)
(entity_class_entry_list
(entity_class_entry
(entity_class))
(entity_class_entry
(entity_class))))
(group_template_declaration
name: (identifier)
(entity_class_entry_list
(entity_class_entry
(entity_class)
(any)))))
====================================
Group declaration - Minimal
====================================
group G1 : E (L2);
---
(design_file
(group_declaration
name: (identifier)
template: (simple_name)
(group_constituent_list
(simple_name))))
====================================
Group declaration - LRM I
====================================
group G1: RESOURCE (L1, L2);
group G2: RESOURCE (L3, L4, L5);
---
(design_file
(group_declaration
name: (identifier)
template: (simple_name)
(group_constituent_list
(simple_name)
(simple_name)))
(group_declaration
name: (identifier)
template: (simple_name)
(group_constituent_list
(simple_name)
(simple_name)
(simple_name))))
====================================
Group declaration - LRM II
====================================
group C2Q: PIN2PIN (PROJECT.GLOBALS.CK, Q);
---
(design_file
(group_declaration
name: (identifier)
template: (simple_name)
(group_constituent_list
(selected_name
prefix: (selected_name
prefix: (simple_name)
suffix: (simple_name))
suffix: (simple_name))
(simple_name))))
====================================
Group declaration - LRM III
====================================
group CONSTRAINT1: DIFF_CYCLES (G1, G3);
---
(design_file
(group_declaration
name: (identifier)
template: (simple_name)
(group_constituent_list
(simple_name)
(simple_name))))

@ -0,0 +1,9 @@
====================
Minimal
====================
type t;
---
(design_file
(incomplete_type_declaration
(identifier)))

@ -0,0 +1,126 @@
====================================
Subprogram - Minimal
====================================
function f is new u;
procedure p is new u;
---
(design_file
(function_instantiation_declaration
designator: (identifier)
uninstantiated: (simple_name))
(procedure_instantiation_declaration
designator: (identifier)
uninstantiated: (simple_name)))
====================================
Subprogram - Signature
====================================
function f is new u [return t];
procedure p is new u [t];
---
(design_file
(function_instantiation_declaration
designator: (identifier)
uninstantiated: (simple_name)
(signature
(return
(type_mark
(simple_name)))))
(procedure_instantiation_declaration
designator: (identifier)
uninstantiated: (simple_name)
(signature
(type_mark
(simple_name)))))
====================================
Subprogram - Generic map aspect
====================================
function f is new u
generic map (a);
procedure p is new u
generic map (a);
---
(design_file
(function_instantiation_declaration
designator: (identifier)
uninstantiated: (simple_name)
(subprogram_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))))))
(procedure_instantiation_declaration
designator: (identifier)
uninstantiated: (simple_name)
(subprogram_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))
============================================
Subprogram - Conflict resolution - Procedure
============================================
procedure p is new u;
procedure p;
---
(design_file
(procedure_instantiation_declaration
designator: (identifier)
uninstantiated: (simple_name))
(procedure_declaration
designator: (identifier)))
============================================
Subprogram - Conflict resolution - Function
============================================
function f is new u;
function f return t;
---
(design_file
(function_instantiation_declaration
designator: (identifier)
uninstantiated: (simple_name))
(function_declaration
designator: (identifier)
(return
(type_mark
(simple_name)))))
====================================
Package - Minimal
====================================
package p is new u;
---
(design_file
(package_instantiation_declaration
name: (identifier)
uninstantiated: (simple_name)))
====================================
Package - Generic map aspect
====================================
package p is new u
generic map (a);
---
(design_file
(package_instantiation_declaration
name: (identifier)
uninstantiated: (simple_name)
(package_map_aspect
(generic_map_aspect
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))

@ -0,0 +1,234 @@
================================================================================
Minimal
================================================================================
constant k: t;
signal s : t;
variable v: t;
file f : ft;
--------------------------------------------------------------------------------
(design_file
(constant_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(signal_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(variable_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(file_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))
================================================================================
Identifier list
================================================================================
constant k1, k2 : t;
signal s1, s2, s3 : t;
variable v1, v2, v3, v4 : t;
file f1, f2, f3, f4, f5 : ft;
--------------------------------------------------------------------------------
(design_file
(constant_declaration
(identifier_list
(identifier)
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(signal_declaration
(identifier_list
(identifier)
(identifier)
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(variable_declaration
(identifier_list
(identifier)
(identifier)
(identifier)
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(file_declaration
(identifier_list
(identifier)
(identifier)
(identifier)
(identifier)
(identifier))
(subtype_indication
(type_mark
(simple_name)))))
================================================================================
Default expression
================================================================================
constant k : t := expr;
signal s : t := expr;
variable v : t := expr;
--------------------------------------------------------------------------------
(design_file
(constant_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(signal_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(variable_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name))))
================================================================================
Shared variable
================================================================================
shared variable sv : t;
--------------------------------------------------------------------------------
(design_file
(shared_variable_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))
================================================================================
Signal kind
================================================================================
signal s : t bus;
signal s : t register;
--------------------------------------------------------------------------------
(design_file
(signal_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(signal_kind))
(signal_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(signal_kind)))
================================================================================
File open information
================================================================================
file f : ft is "fn.ext";
file f : ft open write_mode is "fn.ext";
file f : ft open f(x) is "fn.ext";
--------------------------------------------------------------------------------
(design_file
(file_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(file_open_information
(string_expression
(string_literal))))
(file_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(file_open_information
(file_open_kind
(simple_name))
(string_expression
(string_literal))))
(file_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(file_open_information
(file_open_kind
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))
(string_expression
(string_literal)))))
================================================================================
Type Mark - Selected name [LRM]
================================================================================
signal S : STANDARD.BIT_VECTOR (1 to 10);
--------------------------------------------------------------------------------
(design_file
(signal_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(selected_name
prefix: (simple_name)
suffix: (simple_name)))
(array_constraint
(index_constraint
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))))))
================================================================================
Resolution function [LRM]
================================================================================
signal OUTPUT: WIRED_OR MULTI_VALUED_LOGIC;
--------------------------------------------------------------------------------
(design_file
(signal_declaration
(identifier_list
(identifier))
(subtype_indication
(resolution_function
(simple_name))
(type_mark
(simple_name)))))

@ -0,0 +1,49 @@
====================================
Package declaration - Minimal
====================================
package pkg is
end;
package pkg is
end package;
package pkg is
end pkg;
package pkg is
end package pkg;
---
(design_file
(package_declaration
name: (identifier))
(package_declaration
name: (identifier))
(package_declaration
name: (identifier)
at_end: (simple_name))
(package_declaration
name: (identifier)
at_end: (simple_name)))
==========================
Package body - Minimal
==========================
package body pkg is
end;
package body pkg is
end package body;
package body pkg is
end package body pkg;
---
(design_file
(package_body
package: (simple_name))
(package_body
package: (simple_name))
(package_body
package: (simple_name)
at_end: (simple_name)))

@ -0,0 +1,64 @@
================================================================================
Minimal
================================================================================
type t is
protected
end protected;
type t is
protected
end protected t;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(protected_type_declaration))
(full_type_declaration
name: (identifier)
(protected_type_declaration
at_end: (simple_name))))
================================================================================
LRM I
================================================================================
type SharedCounter is protected
procedure increment (N: Integer := 1);
procedure decrement (N: Integer := 1);
impure function value return Integer;
end protected SharedCounter;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(protected_type_declaration
(declarative_part
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(integer_decimal)))))
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(integer_decimal)))))
(function_declaration
designator: (identifier)
(return
(type_mark
(simple_name)))))
at_end: (simple_name))))

@ -0,0 +1,69 @@
================================================================================
Minimal
================================================================================
type t is
protected body
end protected body;
type t is
protected body
end protected body t;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(protected_type_body))
(full_type_declaration
name: (identifier)
(protected_type_body
at_end: (simple_name))))
================================================================================
LRM I (Simplified)
================================================================================
type SharedCounter is protected body
variable counter: Integer := 0;
procedure increment (N: Integer := 1) is
begin
counter := counter + N;
end procedure increment;
end protected body SharedCounter;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(protected_type_body
(declarative_part
(variable_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(integer_decimal)))
(procedure_body
designator: (identifier)
(procedure_parameter_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(integer_decimal))))
(sequence_of_statements
(simple_variable_assignment
target: (simple_name)
(expression
(simple_expression
(simple_name)
(simple_name)))))
at_end: (simple_name)))
at_end: (simple_name))))

@ -0,0 +1,179 @@
================================================================================
Enumeration type - Minimal
================================================================================
type enum_t is ('a');
type enum_t is (foo);
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(enumeration_type_definition
literal: (character_literal)))
(full_type_declaration
name: (identifier)
(enumeration_type_definition
literal: (identifier))))
================================================================================
Enumeration type - Character type
================================================================================
type enum_t is ('a', foo, bar);
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(enumeration_type_definition
literal: (character_literal)
literal: (identifier)
literal: (identifier))))
================================================================================
Integer type definition
================================================================================
type int_t is range 0 to 255;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(numeric_type_definition
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))))
================================================================================
Floating type definition
================================================================================
type float_t is range 2.0 to 8.0;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(numeric_type_definition
(ascending_range
low: (simple_expression
(real_decimal))
high: (simple_expression
(real_decimal))))))
================================================================================
Physical type definition - Minimal
================================================================================
type phy_t is range l to h
units
p;
end units;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(physical_type_definition
(range_constraint
(ascending_range
low: (simple_expression
(simple_name))
high: (simple_expression
(simple_name))))
(primary_unit_declaration
name: (identifier)))))
================================================================================
Physical type definition
================================================================================
type phy_t is range l to h
units
p;
a = p;
end units;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(physical_type_definition
(range_constraint
(ascending_range
low: (simple_expression
(simple_name))
high: (simple_expression
(simple_name))))
(primary_unit_declaration
name: (identifier))
(secondary_unit_declaration
name: (identifier)
(physical_literal
unit: (simple_name))))))
================================================================================
Physical type definition - LRM
================================================================================
type byte_t is range 0 to 1E16
units
B;
-- decimal
kB = 1000 B;
MB = 1000 kB;
GB = 1000 MB;
TB = 1000 GB;
-- binary
KiB = 1024 B;
MiB = 1024 KiB;
GiB = 1024 MiB;
end units;
--------------------------------------------------------------------------------
(design_file
(full_type_declaration
name: (identifier)
(physical_type_definition
(range_constraint
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))
(primary_unit_declaration
name: (identifier))
(comment)
(secondary_unit_declaration
name: (identifier)
(physical_literal
(integer_decimal)
unit: (simple_name)))
(secondary_unit_declaration
name: (identifier)
(physical_literal
(integer_decimal)
unit: (simple_name)))
(secondary_unit_declaration
name: (identifier)
(physical_literal
(integer_decimal)
unit: (simple_name)))
(secondary_unit_declaration
name: (identifier)
(physical_literal
(integer_decimal)
unit: (simple_name)))
(comment)
(secondary_unit_declaration
name: (identifier)
(physical_literal
(integer_decimal)
unit: (simple_name)))
(secondary_unit_declaration
name: (identifier)
(physical_literal
(integer_decimal)
unit: (simple_name)))
(secondary_unit_declaration
name: (identifier)
(physical_literal
(integer_decimal)
unit: (simple_name))))))

@ -0,0 +1,126 @@
==========================
Procedure - Minimal
==========================
procedure p is
begin
end;
procedure p is
begin
end procedure;
procedure p is
begin
end procedure p;
---
(design_file
(procedure_body
designator: (identifier))
(procedure_body
designator: (identifier))
(procedure_body
designator: (identifier)
at_end: (simple_name)))
==========================
Pure function (implicit) - Minimal
==========================
function f return t is
begin
end;
function f return t is
begin
end function;
function f return t is
begin
end function f;
---
(design_file
(function_body
designator: (identifier)
(return
(type_mark
(simple_name))))
(function_body
designator: (identifier)
(return
(type_mark
(simple_name))))
(function_body
designator: (identifier)
(return
(type_mark
(simple_name)))
at_end: (simple_name)))
==========================
Pure function (explicit) - Minimal
==========================
pure function f return t is
begin
end;
pure function f return t is
begin
end function;
pure function f return t is
begin
end function f;
---
(design_file
(function_body
designator: (identifier)
(return
(type_mark
(simple_name))))
(function_body
designator: (identifier)
(return
(type_mark
(simple_name))))
(function_body
designator: (identifier)
(return
(type_mark
(simple_name)))
at_end: (simple_name)))
==========================
Impure function - Minimal
==========================
impure function f return t is
begin
end;
impure function f return t is
begin
end function;
impure function f return t is
begin
end function f;
---
(design_file
(function_body
designator: (identifier)
(return
(type_mark
(simple_name))))
(function_body
designator: (identifier)
(return
(type_mark
(simple_name))))
(function_body
designator: (identifier)
(return
(type_mark
(simple_name)))
at_end: (simple_name)))

@ -0,0 +1,466 @@
================================================================================
Resolution function
================================================================================
assert new resolved ut;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(resolution_function
(simple_name))
(type_mark
(simple_name)))))))
================================================================================
Record resolution I
================================================================================
assert new (elem resolved) ut;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(record_resolution
(record_element_resolution
element: (simple_name)
(resolution_function
(simple_name))))
(type_mark
(simple_name)))))))
================================================================================
Record resolution II
================================================================================
assert new (elem1 resolved, elem2 resolved) ut;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(record_resolution
(record_element_resolution
element: (simple_name)
(resolution_function
(simple_name)))
(record_element_resolution
element: (simple_name)
(resolution_function
(simple_name))))
(type_mark
(simple_name)))))))
================================================================================
Parenthesized resolution - Resolution function
================================================================================
assert new (resolved) ut;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(parenthesized_resolution
(resolution_function
(simple_name)))
(type_mark
(simple_name)))))))
================================================================================
Parenthesized record resolution
================================================================================
assert new ((elem resolved)) ut;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(parenthesized_resolution
(record_resolution
(record_element_resolution
element: (simple_name)
(resolution_function
(simple_name)))))
(type_mark
(simple_name)))))))
================================================================================
Range constraint I
================================================================================
assert new range_t range l to h;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(range_constraint
(ascending_range
low: (simple_expression
(simple_name))
high: (simple_expression
(simple_name)))))))))
================================================================================
Range constraint II
================================================================================
assert new range_t range st'range;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(range_constraint
(attribute_name
prefix: (simple_name)
designator: (predefined_designator))))))))
================================================================================
Array constraint - Open
================================================================================
assert new arr_t (open);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(array_constraint
(index_constraint
(open))))))))
================================================================================
Array constraint - Discrete Range
================================================================================
assert new arr_t (h downto l);
assert new arr_t (l to h);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(array_constraint
(index_constraint
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name)))))))))
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(array_constraint
(index_constraint
(ascending_range
low: (simple_expression
(simple_name))
high: (simple_expression
(simple_name))))))))))
================================================================================
Record constraint - Array constraint I
================================================================================
assert new rec_t (elem1 (open));
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(record_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(open))))))))))
================================================================================
Record constraint - Array constraint II
================================================================================
assert new rec_t (elem1 (h downto l),
elem2 (l to h));
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(record_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name))))))
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(ascending_range
low: (simple_expression
(simple_name))
high: (simple_expression
(simple_name))))))))))))
================================================================================
Record constraint - Record constraint
================================================================================
assert new rec_t (elem1 (elem2 (open)));
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(record_constraint
(record_element_constraint
element: (simple_name)
(record_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(open))))))))))))
================================================================================
Array element constraint - Array constraint
================================================================================
assert new arr_t (open)(open);
assert new arr_t (open)(open)(open);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(array_constraint
(index_constraint
(open))
(array_element_constraint
(index_constraint
(open))))))))
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(array_constraint
(index_constraint
(open))
(array_element_constraint
(index_constraint
(open))
(array_element_constraint
(index_constraint
(open))))))))))
================================================================================
Array element constraint - Record constraint
================================================================================
assert new arr_t (open)(elem (open));
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(array_constraint
(index_constraint
(open))
(array_element_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(open)))))))))))
================================================================================
Record element constraint - Array constraint
================================================================================
assert new arr_t (elem (open));
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(record_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(open))))))))))
================================================================================
Record element constraint - Record constraint
================================================================================
assert new arr_t (elem (elem (open)));
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(record_constraint
(record_element_constraint
element: (simple_name)
(record_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(open))))))))))))
================================================================================
Array subtype indication
================================================================================
assert new resolved ut(h downto l);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(resolution_function
(simple_name))
(type_mark
(simple_name))
(array_constraint
(index_constraint
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name))))))))))
================================================================================
Record subtype indication
================================================================================
assert new (elem1 resolved, elem2 resolved) ut (elem1 (h downto l),
elem2 (l to h));
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(record_resolution
(record_element_resolution
element: (simple_name)
(resolution_function
(simple_name)))
(record_element_resolution
element: (simple_name)
(resolution_function
(simple_name))))
(type_mark
(simple_name))
(record_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name))))))
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(ascending_range
low: (simple_expression
(simple_name))
high: (simple_expression
(simple_name))))))))))))
================================================================================
Array of records subtype indication
================================================================================
assert new ((elem1 resolved)) ut(h downto l)(elem1 (h downto 0));
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(parenthesized_resolution
(record_resolution
(record_element_resolution
element: (simple_name)
(resolution_function
(simple_name)))))
(type_mark
(simple_name))
(array_constraint
(index_constraint
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name))))
(array_element_constraint
(record_element_constraint
element: (simple_name)
(array_constraint
(index_constraint
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(integer_decimal)))))))))))))

@ -0,0 +1,116 @@
================================================================================
Minimal [LRM]
================================================================================
assert new Node;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name)))))))
================================================================================
Qualified expression I [LRM]
================================================================================
assert new Node'(Delay => 5 ns,
\Next\ => Stack);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(qualified_expression
(type_mark
(simple_name))
(aggregate
(named_element_association
(choices
(simple_expression
(simple_name)))
(expression
(physical_literal
(integer_decimal)
unit: (simple_name))))
(named_element_association
(choices
(simple_expression
(extended_simple_name)))
(expression
(simple_name)))))))))
================================================================================
Qualified expression II [LRM]
================================================================================
assert new CELL'(0, null, null);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(qualified_expression
(type_mark
(simple_name))
(aggregate
(positional_element_association
(expression
(integer_decimal)))
(positional_element_association
(expression
(null)))
(positional_element_association
(expression
(null)))))))))
================================================================================
Subtype indication LRM - I
================================================================================
assert new String;
assert new String (1 to 10);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(array_constraint
(index_constraint
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))))))))
================================================================================
Subtype indication - LRM II
================================================================================
assert new bit_vector (1 to index);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(allocator
(subtype_indication
(type_mark
(simple_name))
(array_constraint
(index_constraint
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(simple_name))))))))))

@ -0,0 +1,273 @@
===================================
Factor
===================================
t <= abs a,
not b;
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(factor
(simple_name))))
(waveform_element
(expression
(factor
(simple_name)))))))
===================================
Factor - exponentiation
===================================
t <= a**b;
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(exponentiation
(simple_name)
(simple_name)))))))
===================================
Factor - logical reduction operation
===================================
t <= and a,
or a,
nand a,
nor a,
xor a,
xnor a;
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(reduction
(simple_name))))
(waveform_element
(expression
(reduction
(simple_name))))
(waveform_element
(expression
(reduction
(simple_name))))
(waveform_element
(expression
(reduction
(simple_name))))
(waveform_element
(expression
(reduction
(simple_name))))
(waveform_element
(expression
(reduction
(simple_name)))))))
===================================
Associative logical expression
===================================
t <= a and b and c;
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(logical_expression
(simple_name)
(simple_name)
(simple_name)))))))
===================================
Term I
===================================
t <= a * b,
a / b,
a mod b,
a rem b;
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(term
(simple_name)
(simple_name))))
(waveform_element
(expression
(term
(simple_name)
(simple_name))))
(waveform_element
(expression
(term
(simple_name)
(simple_name))))
(waveform_element
(expression
(term
(simple_name)
(simple_name)))))))
===================================
Term II
===================================
t <= a * b / c mod d rem e;
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(term
(simple_name)
(simple_name)
(simple_name)
(simple_name)
(simple_name)))))))
===================================
Simple expression
===================================
t <= a + b - c;
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_expression
(simple_name)
(simple_name)
(simple_name)))))))
===================================
Simple expression - Sign
===================================
t <= -a, -b;
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(sign
(simple_name))))
(waveform_element
(expression
(sign
(simple_name)))))))
===================================
Sign
===================================
t <= - a * b,
- abs a,
- abs b,
- a ** b;
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(sign
(term
(simple_name)
(simple_name)))))
(waveform_element
(expression
(sign
(factor
(simple_name)))))
(waveform_element
(expression
(sign
(factor
(simple_name)))))
(waveform_element
(expression
(sign
(exponentiation
(simple_name)
(simple_name))))))))
===================================
Parenthesized expression I
===================================
t <= (x);
t <= ((x));
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(parenthesized_expression
(simple_name))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(parenthesized_expression
(parenthesized_expression
(simple_name))))))))
===================================
Parenthesized expression II
===================================
t <= (x(foo'range));
t <= ((x(foo'range)));
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(parenthesized_expression
(slice_name
prefix: (simple_name)
(attribute_name
prefix: (simple_name)
designator: (predefined_designator))))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(parenthesized_expression
(parenthesized_expression
(slice_name
prefix: (simple_name)
(attribute_name
prefix: (simple_name)
designator: (predefined_designator))))))))))

@ -0,0 +1,86 @@
================================================================================
VHDL LRM 9.1 NOTE 2
================================================================================
assert (and A) and B;
assert A and (and B);
assert and (and A);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(logical_expression
(parenthesized_expression
(reduction
(simple_name)))
(simple_name))))
(assertion_statement
(conditional_expression
(logical_expression
(simple_name)
(parenthesized_expression
(reduction
(simple_name))))))
(assertion_statement
(conditional_expression
(reduction
(parenthesized_expression
(reduction
(simple_name)))))))
================================================================================
VHDL LRM 9.2.7 NOTE
================================================================================
assert -5 rem 2 >= 0;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(relation
(sign
(term
(integer_decimal)
(integer_decimal)))
(integer_decimal)))))
================================================================================
VHDL LRM 9.2.6 NOTE
================================================================================
assert A/(+B) > 0;
assert A**(-B) > 0;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(relation
(term
(simple_name)
(parenthesized_expression
(sign
(simple_name))))
(integer_decimal))))
(assertion_statement
(conditional_expression
(relation
(exponentiation
(simple_name)
(parenthesized_expression
(sign
(simple_name))))
(integer_decimal)))))
================================================================================
ADA LRM 4.5.0
================================================================================
assert not Sunny or Warm;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(logical_expression
(factor
(simple_name))
(simple_name)))))

@ -0,0 +1,264 @@
================================================================================
Factor + Term
================================================================================
t <= abs a * not b;
t <= abs a * not b * not c;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(term
(factor
(simple_name))
(factor
(simple_name)))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(term
(factor
(simple_name))
(factor
(simple_name))
(factor
(simple_name))))))))
================================================================================
Factor + Simple Expression
================================================================================
t <= abs a + not b;
t <= abs a + not b + not c;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_expression
(factor
(simple_name))
(factor
(simple_name)))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_expression
(factor
(simple_name))
(factor
(simple_name))
(factor
(simple_name))))))))
================================================================================
Factor + Shift Expression
================================================================================
t <= not a sll abs b;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(shift_expression
(factor
(simple_name))
(factor
(simple_name))))))))
================================================================================
Exponentiation + Term
================================================================================
t <= a**1 * b**2;
t <= a**1 * b**2 * c**3;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(term
(exponentiation
(simple_name)
(integer_decimal))
(exponentiation
(simple_name)
(integer_decimal)))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(term
(exponentiation
(simple_name)
(integer_decimal))
(exponentiation
(simple_name)
(integer_decimal))
(exponentiation
(simple_name)
(integer_decimal))))))))
================================================================================
Exponentiation + Simple Expression
================================================================================
t <= a**1 + b**2;
t <= a**1 + b**2 + c**3;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_expression
(exponentiation
(simple_name)
(integer_decimal))
(exponentiation
(simple_name)
(integer_decimal)))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_expression
(exponentiation
(simple_name)
(integer_decimal))
(exponentiation
(simple_name)
(integer_decimal))
(exponentiation
(simple_name)
(integer_decimal))))))))
================================================================================
Exponentiation + Shift Expression
================================================================================
t <= a**1 sll b**2;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(shift_expression
(exponentiation
(simple_name)
(integer_decimal))
(exponentiation
(simple_name)
(integer_decimal))))))))
================================================================================
Exponentiation + Factor + Term
================================================================================
t <= abs lhs * a**1;
t <= a**1 * not a;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(term
(factor
(simple_name))
(exponentiation
(simple_name)
(integer_decimal)))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(term
(exponentiation
(simple_name)
(integer_decimal))
(factor
(simple_name))))))))
================================================================================
Exponentiation + Factor + Simple Expression
================================================================================
t <= abs lhs + a**1;
t <= a**1 + not a;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_expression
(factor
(simple_name))
(exponentiation
(simple_name)
(integer_decimal)))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(simple_expression
(exponentiation
(simple_name)
(integer_decimal))
(factor
(simple_name))))))))
================================================================================
Exponentiation + Factor + Simple Expression
================================================================================
t <= abs lhs sll a**1;
t <= a**1 sll abs a;
--------------------------------------------------------------------------------
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(shift_expression
(factor
(simple_name))
(exponentiation
(simple_name)
(integer_decimal)))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(shift_expression
(exponentiation
(simple_name)
(integer_decimal))
(factor
(simple_name))))))))

@ -0,0 +1,54 @@
==========================================================
Parenthesized expression
==========================================================
assert foo'(a);
---
(design_file
(assertion_statement
(conditional_expression
(qualified_expression
(type_mark
(simple_name))
(expression
(simple_name))))))
==========================================================
Aggregate - Positional asssociation
==========================================================
assert foo'(a,b);
---
(design_file
(assertion_statement
(conditional_expression
(qualified_expression
(type_mark
(simple_name))
(aggregate
(positional_element_association
(expression
(simple_name)))
(positional_element_association
(expression
(simple_name))))))))
==========================================================
Aggregate - Named asssociation
==========================================================
assert foo'(a=>b);
---
(design_file
(assertion_statement
(conditional_expression
(qualified_expression
(type_mark
(simple_name))
(aggregate
(named_element_association
(choices
(simple_expression
(simple_name)))
(expression
(simple_name))))))))

@ -0,0 +1,57 @@
=========================
Attribute name
=========================
report integer'image(a);
---
(design_file
(report_statement
(string_expression
(attribute_name
prefix: (simple_name)
designator: (predefined_designator)
(expression
(simple_name))))))
=========================
Function
=========================
report to_string(a);
---
(design_file
(report_statement
(string_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))
=========================
Concatenation
=========================
report "a" & "b";
---
(design_file
(report_statement
(string_expression
(concatenation
(string_literal)
(string_literal)))))
=========================
Concatenation II
=========================
report "a" & "b" & "c";
---
(design_file
(report_statement
(string_expression
(concatenation
(string_literal)
(string_literal)
(string_literal)))))

@ -0,0 +1,357 @@
============================================================================
Constant interface declarations
============================================================================
function f (constant k : t;
constant k : in i;
k : t;
k : in t) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))
(return
(type_mark
(simple_name)))))
============================================================================
Signal interface declarations
============================================================================
function f (signal s1 : t;
signal s2 : in t) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))
(return
(type_mark
(simple_name)))))
============================================================================
File interface declarations
============================================================================
function f (file f : t) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(file_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))
(return
(type_mark
(simple_name)))))
============================================================================
LINT: Illegal constant interface declarations
============================================================================
function f (constant k : out t;
constant k : inout t;
constant k : buffer t;
constant k : linkage t) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))
(return
(type_mark
(simple_name)))))
============================================================================
LINT: Illegal signal interface declarations
============================================================================
function f (signal s : t := x;
signal s : in t := x;
signal s : out t;
signal s : inout t;
signal s : buffer t;
signal s : linkage t) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))
(return
(type_mark
(simple_name)))))
============================================================================
LINT: Illegal variable interface declarations
============================================================================
function f (variable v : in t;
variable v : out t;
variable v : inout t;
variable v : buffer t;
variable v : linkage t) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))
(return
(type_mark
(simple_name)))))
============================================================================
LINT: Illegal file interface declarations
============================================================================
function f (file f : in t;
file f : out t;
file f : inout t;
file f : buffer t;
file f : linkage t) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))
(return
(type_mark
(simple_name)))))
============================================================================
LINT: Illegal type interface declarations
============================================================================
function f (type t) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(type_interface_declaration
(identifier)))
(return
(type_mark
(simple_name)))))
============================================================================
LINT: Illegal subprogram interface declarations
============================================================================
function f (procedure p) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(procedure_interface_declaration
(identifier)))
(return
(type_mark
(simple_name)))))
============================================================================
LINT: Illegal package interface declarations
============================================================================
function f (package pkg is new pkg generic map (<>)) return t;
---
(design_file
(function_declaration
(identifier)
(function_parameter_clause
(package_interface_declaration
(identifier)
(simple_name)
(package_map_aspect
(generic_map_aspect
(any)))))
(return
(type_mark
(simple_name)))))

@ -0,0 +1,410 @@
============================================================================
Entity declaration
============================================================================
entity e is
generic (k : t);
end entity e;
---
(design_file
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name))))
============================================================================
Block statement
============================================================================
B1:
block
generic (k : t);
begin
end block B1;
---
(design_file
(block_statement
(label
(identifier))
(block_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
============================================================================
Component declaration
============================================================================
component c
generic (s : t);
end component c;
---
(design_file
(component_declaration
name: (identifier)
(component_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
============================================================================
Package declaration
============================================================================
package pkg is
generic (k : t)
end package pkg;
---
(design_file
(package_declaration
name: (identifier)
(package_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))))
at_end: (simple_name)))
============================================================================
Subprogram specification
============================================================================
procedure p
generic (k:t);
---
(design_file
(procedure_declaration
designator: (identifier)
(subprogram_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))))))
============================================================================
Legal interface declarations
============================================================================
entity e is
generic (constant k : t;
constant k : in i;
k : t;
k : in t);
end entity e;
entity e is
generic (type t);
end entity e;
entity e is
generic (procedure p);
end entity e;
entity e is
generic (package pkg is new upkg generic map (<>));
end entity e;
---
(design_file
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(type_interface_declaration
name: (identifier))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(procedure_interface_declaration
designator: (identifier))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(package_interface_declaration
name: (identifier)
uninstantiated: (simple_name)
(package_map_aspect
(generic_map_aspect
(any))))
(semicolon)))
at_end: (simple_name))))
============================================================================
LINT: Illegal interface declarations
============================================================================
entity e is
generic (constant k : out t;
constant k : inout t;
constant k : buffer t;
constant k : linkage t);
end entity e;
entity e is
generic (signal s : t;
signal s : in t;
signal s : out t;
signal s : inout t;
signal s : buffer t;
signal s : linkage t);
end entity e;
entity e is
generic (variable v : t;
variable v : in t;
variable v : out t;
variable v : inout t;
variable v : buffer t;
variable v : linkage t);
end entity e;
entity e is
generic (file v : in t;
file v : out t;
file v : inout t;
file v : buffer t;
file v : linkage t);
end entity e;
---
(design_file
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(variable_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name))))

@ -0,0 +1,31 @@
============================================================================
Package interface generic map aspect
============================================================================
entity e is
generic (
package p1 is new up generic map (default);
package p2 is new up generic map (<>)
);
end entity e;
---
(design_file
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(package_interface_declaration
name: (identifier)
uninstantiated: (simple_name)
(package_map_aspect
(generic_map_aspect
(default))))
(package_interface_declaration
name: (identifier)
uninstantiated: (simple_name)
(package_map_aspect
(generic_map_aspect
(any))))
(semicolon)))
at_end: (simple_name))))

@ -0,0 +1,379 @@
============================================================================
Entity declaration
============================================================================
entity e is
port (s : t);
end entity e;
---
(design_file
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name))))
============================================================================
Block statements
============================================================================
B1:
block
port (s : t);
begin
end block B1;
---
(design_file
(block_statement
(label
(identifier))
(block_header
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
============================================================================
Component declaration
============================================================================
component c
port (s : t);
end component c;
---
(design_file
(component_declaration
name: (identifier)
(component_header
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
============================================================================
Legal interface declarations
============================================================================
entity e is
port (signal s : in t;
signal s : out t;
signal s : inout t;
signal s : buffer t;
signal s : linkage t;
s : in t;
s : out t;
s : inout t;
s : buffer t;
s : linkage t;
s : t);
end entity e;
---
(design_file
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(port_clause
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name))))
============================================================================
LINT: Illegal interface declarations
============================================================================
entity e is
port (constant k : in t;
constant k : out t;
constant k : inout t;
constant k : buffer t;
constant k : linkage t;
constant k : t);
end entity e;
entity e is
port (variable v : in t;
variable v : out t;
variable v : inout t;
variable v : buffer t;
variable v : linkage t;
variable v : t);
end entity e;
entity e is
port (file v : in t;
file v : out t;
file v : inout t;
file v : buffer t;
file v : linkage t;
file v : t);
end entity e;
entity e is
port (procedure p);
end entity e;
entity e is
port (package pkg is new upkg generic map (<>));
end entity e;
---
(design_file
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(port_clause
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(port_clause
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(port_clause
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(port_clause
(procedure_interface_declaration
designator: (identifier))
(semicolon)))
at_end: (simple_name)))
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(port_clause
(package_interface_declaration
name: (identifier)
uninstantiated: (simple_name)
(package_map_aspect
(generic_map_aspect
(any))))
(semicolon)))
at_end: (simple_name))))

@ -0,0 +1,395 @@
============================================================================
Constant interface declarations
============================================================================
procedure f (constant k : t;
constant k : in i;
k : t;
k : in t);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))))
============================================================================
Signal interface declarations
============================================================================
procedure f (signal s : t;
signal s : in t;
signal s : out t;
signal s : inout t);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))))
============================================================================
Variable interface declarations
============================================================================
procedure f (variable v : in t := x;
variable k : out t;
variable k : inout t;
k : out t;
k : inout t);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))))
============================================================================
File interface declarations
============================================================================
procedure f (file f : t);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(file_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))))))
============================================================================
LINT: Illegal constant interface declarations
============================================================================
procedure f (constant k : out t;
constant k : inout t;
constant k : buffer t;
constant k : linkage t);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(constant_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))))
============================================================================
LINT: Illegal signal interface declarations
============================================================================
procedure f (signal s : t := x;
signal s : in t := x;
signal s : out t := x;
signal s : inout t := x;
signal s : buffer t;
signal s : linkage t);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(signal_interface_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(signal_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))))
============================================================================
LINT: Illegal variable interface declarations
============================================================================
procedure f (variable k : out t := x;
variable k : inout t := x;
variable k : buffer t;
variable k : linkage t);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))
(default_expression
(simple_name)))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(variable_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))))
============================================================================
LINT: Illegal file interface declarations
============================================================================
procedure f (file v : in t;
file v : out t;
file v : inout t;
file v : buffer t;
file v : linkage t);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name))))
(file_interface_declaration
(identifier_list
(identifier))
(mode)
(subtype_indication
(type_mark
(simple_name)))))))
============================================================================
LINT: Illegal type interface declarations
============================================================================
procedure f (type t);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(type_interface_declaration
name: (identifier)))))
============================================================================
LINT: Illegal subprogram interface declarations
============================================================================
procedure f (procedure p);
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(procedure_interface_declaration
designator: (identifier)))))
============================================================================
LINT: Illegal package interface declarations
============================================================================
procedure f (package pkg is new pkg generic map (<>));
---
(design_file
(procedure_declaration
designator: (identifier)
(procedure_parameter_clause
(package_interface_declaration
name: (identifier)
uninstantiated: (simple_name)
(package_map_aspect
(generic_map_aspect
(any)))))))

@ -0,0 +1,33 @@
============================================================================
Interface subprogram default
============================================================================
entity e is
generic (impure function f1 return t is <>;
pure function f2 return t is foo.bar);
end;
---
(design_file
(design_unit
(entity_declaration
name: (identifier)
(entity_header
(generic_clause
(function_interface_declaration
designator: (identifier)
(return
(type_mark
(simple_name)))
(interface_subprogram_default
(same)))
(function_interface_declaration
designator: (identifier)
(return
(type_mark
(simple_name)))
(interface_subprogram_default
(selected_name
prefix: (simple_name)
suffix: (simple_name))))
(semicolon))))))

@ -0,0 +1,295 @@
============================================
Positional association
============================================
assert (a,b);
assert (a,b,c);
---
(design_file
(assertion_statement
(conditional_expression
(aggregate
(positional_element_association
(expression
(simple_name)))
(positional_element_association
(expression
(simple_name))))))
(assertion_statement
(conditional_expression
(aggregate
(positional_element_association
(expression
(simple_name)))
(positional_element_association
(expression
(simple_name)))
(positional_element_association
(expression
(simple_name)))))))
============================================
Named association
============================================
assert (a=>b,c=>d,e=>f);
---
(design_file
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(simple_expression
(simple_name)))
(expression
(simple_name)))
(named_element_association
(choices
(simple_expression
(simple_name)))
(expression
(simple_name)))
(named_element_association
(choices
(simple_expression
(simple_name)))
(expression
(simple_name)))))))
============================================
Choices
============================================
assert (a|b|c=>d);
---
(design_file
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(simple_expression
(simple_name))
(simple_expression
(simple_name))
(simple_expression
(simple_name)))
(expression
(simple_name)))))))
============================================
Others
============================================
assert (others=>a);
assert (a,b=>c,others=>d);
---
(design_file
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(others))
(expression
(simple_name))))))
(assertion_statement
(conditional_expression
(aggregate
(positional_element_association
(expression
(simple_name)))
(named_element_association
(choices
(simple_expression
(simple_name)))
(expression
(simple_name)))
(named_element_association
(choices
(others))
(expression
(simple_name)))))))
============================================
Mixed element associations
============================================
assert (a,b=>c);
assert (a,b,c=>d,e=>f);
assert (a,b,c|d=>e,f|g=>h);
---
(design_file
(assertion_statement
(conditional_expression
(aggregate
(positional_element_association
(expression
(simple_name)))
(named_element_association
(choices
(simple_expression
(simple_name)))
(expression
(simple_name))))))
(assertion_statement
(conditional_expression
(aggregate
(positional_element_association
(expression
(simple_name)))
(positional_element_association
(expression
(simple_name)))
(named_element_association
(choices
(simple_expression
(simple_name)))
(expression
(simple_name)))
(named_element_association
(choices
(simple_expression
(simple_name)))
(expression
(simple_name))))))
(assertion_statement
(conditional_expression
(aggregate
(positional_element_association
(expression
(simple_name)))
(positional_element_association
(expression
(simple_name)))
(named_element_association
(choices
(simple_expression
(simple_name))
(simple_expression
(simple_name)))
(expression
(simple_name)))
(named_element_association
(choices
(simple_expression
(simple_name))
(simple_expression
(simple_name)))
(expression
(simple_name)))))))
============================================
Aggregate name on choice
============================================
assert (a'high=>b);
---
(design_file
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(simple_expression
(attribute_name
prefix: (simple_name)
designator: (predefined_designator))))
(expression
(simple_name)))))))
============================================
Discrete range I
============================================
assert (h downto l=>a);
assert (l to h=>a);
---
(design_file
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name))))
(expression
(simple_name))))))
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(ascending_range
low: (simple_expression
(simple_name))
high: (simple_expression
(simple_name))))
(expression
(simple_name)))))))
============================================
Discrete range II
============================================
assert (t'range=>a);
assert (t'reverse_range=>a);
---
(design_file
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(attribute_name
prefix: (simple_name)
designator: (predefined_designator)))
(expression
(simple_name))))))
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(attribute_name
prefix: (simple_name)
designator: (predefined_designator)))
(expression
(simple_name)))))))
============================================
Discrete range III
============================================
assert (t'range(1)=>a);
assert (t'reverse_range(1)=>a);
---
(design_file
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(attribute_name
prefix: (simple_name)
designator: (predefined_designator)
(expression
(integer_decimal))))
(expression
(simple_name))))))
(assertion_statement
(conditional_expression
(aggregate
(named_element_association
(choices
(attribute_name
prefix: (simple_name)
designator: (predefined_designator)
(expression
(integer_decimal))))
(expression
(simple_name)))))))

@ -0,0 +1,145 @@
============================================
Minimal
============================================
assert b"";
assert o"";
assert x"";
assert ub"";
assert uo"";
assert ux"";
assert sb"";
assert so"";
assert sx"";
---
(design_file
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal))))
============================================
Length
============================================
assert 4b"0";
assert 8ub"0";
assert 16sb"0";
assert 04o"0";
assert 08uo"0";
assert 016so"0";
assert 004x"0";
assert 008ux"0";
assert 0016sx"0";
---
(design_file
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal))))
============================================
Bit value
============================================
assert b"01";
assert ub"01";
assert sb"01";
assert o"0123_4567";
assert uo"0123_4567";
assert so"0123_4567";
assert x"0123_4567";
assert ux"0123_4567_89AB_CDEF";
assert sx"0123_4567_89AB_CDEF";
---
(design_file
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal)))
(assertion_statement
(conditional_expression
(bit_string_literal))))
============================================
std_match
============================================
assert b"--";
---
(design_file
(assertion_statement
(conditional_expression
(bit_string_literal))))

@ -0,0 +1,59 @@
===========================
Minimal
===========================
--
---
(design_file
(comment))
===========================
Multi line - Minimal
===========================
/**/
---
(design_file
(comment))
===========================
Multi line - Single line
===========================
/**/
/***/
/****/
/***/
/**/
---
(design_file
(comment)
(comment)
(comment)
(comment)
(comment))
===========================
Multi line - Multiple lines
===========================
/*
*/
---
(design_file
(comment))
===========================
Multi line - Banner
===========================
/********************************
*********************************/
---
(design_file
(comment))

@ -0,0 +1,10 @@
============================================
Null literal
============================================
assert null;
---
(design_file
(assertion_statement
(conditional_expression
(null))))

@ -0,0 +1,366 @@
======================================================================
Integer decimal literals
======================================================================
assert 0;
assert 0000;
assert 1;
assert 1234;
assert 00_00;
assert 12_34;
---
(design_file
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal))))
======================================================================
Integer decimal literals - Exponent
======================================================================
assert 0e0;
assert 0000e0;
assert 1e1;
assert 1234e1234;
assert 00_00e0;
assert 12_34e+1;
assert 12_34e+1234;
---
(design_file
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal)))
(assertion_statement
(conditional_expression
(integer_decimal))))
======================================================================
Real decimal literals
======================================================================
assert 0.0;
assert 00.0;
assert 1.0;
assert 12.34;
assert 00_00.0000;
assert 12_34.5678;
assert 00_00.00_00;
assert 12_34.56_78;
---
(design_file
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal))))
======================================================================
Real decimal literals - Negative exponent
======================================================================
assert 1.0e-1;
assert 12.34e-1234;
assert 12_34.5678e-1;
assert 12_34.56_78e-1245;
assert 12_34.56_78e-1;
assert 12_34.56_78e-1245;
---
(design_file
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal)))
(assertion_statement
(conditional_expression
(real_decimal))))
======================================================================
Integer based literals - Base I
======================================================================
assert 2#0#;
assert 8#0#;
assert 010#0#;
assert 016#0#;
---
(design_file
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer))))
======================================================================
Integer based literals - Based integer I
======================================================================
assert 2#1#;
assert 3#2#;
assert 4#3#;
assert 5#4#;
assert 6#5#;
assert 7#6#;
assert 8#7#;
assert 9#8#;
assert 10#9#;
assert 11#A#;
assert 12#B#;
assert 13#C#;
assert 14#D#;
assert 15#E#;
assert 16#F#;
---
(design_file
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer))))
======================================================================
Integer based literals - Exponent
======================================================================
assert 16#e1#e1;
assert 16#e1#e+1;
assert 16#e1#e-1;
---
(design_file
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer)))
(assertion_statement
(conditional_expression
(based_integer))))
======================================================================
Real based literals
======================================================================
assert 2#0.0#;
assert 16#0.0#;
assert 16#01234567.89abcdef#;
assert 16#01234567.89ABCDEF#;
---
(design_file
(assertion_statement
(conditional_expression
(based_real)))
(assertion_statement
(conditional_expression
(based_real)))
(assertion_statement
(conditional_expression
(based_real)))
(assertion_statement
(conditional_expression
(based_real))))
======================================================================
Real based literals - Positive exponent
======================================================================
assert 16#E1.E1#E1;
assert 16#E1.E1#E+1;
assert 16#E1.E1#E-1;
---
(design_file
(assertion_statement
(conditional_expression
(based_real)))
(assertion_statement
(conditional_expression
(based_real)))
(assertion_statement
(conditional_expression
(based_real))))
======================================================================
Physical literals I
======================================================================
assert 100 ns;
assert 16#E1#E1 MIN;
---
(design_file
(assertion_statement
(conditional_expression
(physical_literal
(integer_decimal)
(simple_name))))
(assertion_statement
(conditional_expression
(physical_literal
(based_integer)
(simple_name)))))
======================================================================
Physical literals II
======================================================================
assert 100ns;
assert 16#E1#E1MIN;
---
(design_file
(assertion_statement
(conditional_expression
(physical_literal
(integer_decimal)
unit: (simple_name))))
(assertion_statement
(conditional_expression
(physical_literal
(based_integer)
unit: (simple_name)))))
======================================================================
Physical literals - Integer coefficient
======================================================================
assert 1 E1;
assert 2e+2 E1;
assert 16#E1# E1;
assert 16#E1#E1 E1;
---
(design_file
(assertion_statement
(conditional_expression
(physical_literal
(integer_decimal)
unit: (simple_name))))
(assertion_statement
(conditional_expression
(physical_literal
(integer_decimal)
unit: (simple_name))))
(assertion_statement
(conditional_expression
(physical_literal
(based_integer)
unit: (simple_name))))
(assertion_statement
(conditional_expression
(physical_literal
(based_integer)
unit: (simple_name)))))

@ -0,0 +1,332 @@
==============================================================
Character literal - White spaces (SPACE and NBSP)
==============================================================
report ' ' & ' ';
---
(design_file
(report_statement
(string_expression
(concatenation
(character_literal)
(character_literal)))))
==============================================================
Character literal - Apostrophe
==============================================================
report ''' & ''';
---
(design_file
(report_statement
(string_expression
(concatenation
(character_literal)
(character_literal)))))
==============================================================
Character literal - Quotation mark
==============================================================
report '"' & '"';
---
(design_file
(report_statement
(string_expression
(concatenation
(character_literal)
(character_literal)))))
==============================================================
Character literal - Backtick
==============================================================
report '`';
---
(design_file
(report_statement
(string_expression
(character_literal))))
==============================================================
Character literal - Solidus and backslash
==============================================================
report '/' & '\';
---
(design_file
(report_statement
(string_expression
(concatenation
(character_literal)
(character_literal)))))
==============================================================
Character literal - Number signal
==============================================================
report '#' & 'e';
---
(design_file
(report_statement
(string_expression
(concatenation
(character_literal)
(character_literal)))))
==============================================================
Character literal - STD_LOGIC values (upper case)
==============================================================
report '1' & '0' & 'U' & 'X' & 'W' & 'L' & 'H' & '-';
---
(design_file
(report_statement
(string_expression
(concatenation
(character_literal)
(character_literal)
(character_literal)
(character_literal)
(character_literal)
(character_literal)
(character_literal)
(character_literal)))))
==============================================================
Character literal - STD_LOGIC values (lower case)
==============================================================
report '1' & '0' & 'u' & 'x' & 'w' & 'l' & 'h' & '-';
---
(design_file
(report_statement
(string_expression
(concatenation
(character_literal)
(character_literal)
(character_literal)
(character_literal)
(character_literal)
(character_literal)
(character_literal)
(character_literal)))))
==============================================================
Special characters
==============================================================
report '"';
report '!';
report '$';
report '%';
report '\';
report '^';
report '{';
report '}';
report ''';
report '~';
report '¡';
report '¢';
report '£';
report '¤';
report '¥';
report '¦';
report '§';
report '¨';
report '©';
report 'ª';
report '«';
report '¬';
report '®';
report '¯';
report '°';
report '±';
report '²';
report '³';
report '´';
report 'µ';
report '¶';
report '·';
report '¸';
report '¹';
report 'º';
report '»';
report '¼';
report '½';
report '¾';
report '¿';
report '×';
report '÷';
report '-';
---
(design_file
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal)))
(report_statement
(string_expression
(character_literal))))
==============================================================
Character literal - ASCII mnemonics (simple_names)
==============================================================
report nul;
report ack & nak;
report ack & nak;
report esc & esc;
report ht & vt & cr & lf & ff;
---
(design_file
(report_statement
(string_expression
(simple_name)))
(report_statement
(string_expression
(concatenation
(simple_name)
(simple_name))))
(report_statement
(string_expression
(concatenation
(simple_name)
(simple_name))))
(report_statement
(string_expression
(concatenation
(simple_name)
(simple_name))))
(report_statement
(string_expression
(concatenation
(simple_name)
(simple_name)
(simple_name)
(simple_name)
(simple_name)))))

@ -0,0 +1,207 @@
============================================
Minimal
============================================
report "";
---
(design_file
(report_statement
(string_expression
(string_literal))))
============================================
White space (SPACE)
============================================
report " ";
---
(design_file
(report_statement
(string_expression
(string_literal))))
============================================
White space (NBSP)
============================================
report " ";
---
(design_file
(report_statement
(string_expression
(string_literal))))
==============================================================
Apostrophe
==============================================================
report "'";
---
(design_file
(report_statement
(string_expression
(string_literal))))
==============================================================
Quotation mark (escape)
==============================================================
report """";
---
(design_file
(report_statement
(string_expression
(string_literal))))
==============================================================
Underscore
==============================================================
report "_";
---
(design_file
(report_statement
(string_expression
(string_literal))))
==============================================================
Backslash
==============================================================
report "\";
---
(design_file
(report_statement
(string_expression
(string_literal))))
==============================================================
Comment
==============================================================
report "--";
---
(design_file
(report_statement
(string_expression
(string_literal))))
==============================================================
Multi line comment
==============================================================
report "/*aa*/";
---
(design_file
(report_statement
(string_expression
(string_literal))))
==============================================================
Zeros and ones
==============================================================
report "010";
---
(design_file
(report_statement
(string_expression
(string_literal))))
==============================================================
Operators symbols
==============================================================
report "and";
report ">=";
report "sll";
report "+";
report "abs";
report "**";
---
(design_file
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal))))
==============================================================
Regex Tokens
==============================================================
report "^";
report "$";
report ".";
report "|";
report "\";
report "*";
report "?";
report "+";
report "[";
report "]";
report "(";
report ")";
report "{";
report "}";
report "#";
---
(design_file
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal)))
(report_statement
(string_expression
(string_literal))))

@ -0,0 +1,160 @@
==============================================================
Ambiguity I
==============================================================
-- possible interpretations:
-- (function_call
-- (function_name "foo")
-- (_name "bar"))
--
-- (type_conversion
-- (type_name "foo")
-- (_name "bar"))
--
-- (indexed_name
-- (array_name "foo")
-- (_name "bar"))
--
-- (slice_name
-- (array_name "foo")
-- (subtype_name "bar"))
assert foo(bar);
---
(design_file
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))
==============================================================
Ambiguity II
==============================================================
-- Possible interpretations:
-- (function_call
-- (function_name "foo")
-- (_name "bar")
-- (_name "baz"))
--
-- (indexed_name
-- (array_name "foo")
-- (_name "bar")
-- (_name "baz"))
assert foo(bar, baz);
---
(design_file
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))
(expression
(simple_name)))))))
==============================================================
Ambiguity III
==============================================================
-- Possible interpretations:
-- (slice_name
-- (function_call ...)
-- (subtype_name "bar"))
--
-- (indexed_name
-- (function_call ...)
-- (object_name "bar"))
assert foobar(foo=>bar)(bar);
---
(design_file
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(comment)
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (function_call
function: (simple_name)
(association_list
(named_association_element
formal_part: (simple_name)
actual_part: (expression
(simple_name)))))
(expression_list
(expression
(simple_name)))))))
==============================================================
Ambiguous name on ambiguous name
==============================================================
assert foo(bar(x));
---
(design_file
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))))))))))
==============================================================
PSL Built-ins functions names (not reserved words)
==============================================================
t <= prev(x);
---
(design_file
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))))

@ -0,0 +1,52 @@
=============================
Attribute of attribute
=============================
assert t'base'left;
---
(design_file
(assertion_statement
(conditional_expression
(attribute_name
prefix: (attribute_name
prefix: (simple_name)
designator: (predefined_designator))
designator: (predefined_designator)))))
=============================
External name
=============================
assert << constant a : foo >>'subtype;
---
(design_file
(assertion_statement
(conditional_expression
(attribute_name
prefix: (external_constant_name
(relative_pathname
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))
designator: (predefined_designator)))))
=============================
Function call
=============================
assert foo(a => b)'high;
---
(design_file
(assertion_statement
(conditional_expression
(attribute_name
prefix: (function_call
function: (simple_name)
(association_list
(named_association_element
formal_part: (simple_name)
actual_part: (expression
(simple_name)))))
designator: (predefined_designator)))))

@ -0,0 +1,292 @@
================================================================================
Object classes
================================================================================
assert << constant obj : bar_t >>;
assert << signal obj : bar_t >>;
assert << variable obj : bar_t >>;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(external_constant_name
(relative_pathname
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_signal_name
(relative_pathname
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_variable_name
(relative_pathname
object: (simple_name))
(subtype_indication
(type_mark
(simple_name)))))))
================================================================================
Package pathname
================================================================================
assert << constant @lib.pkg.obj : foo_t >>;
assert << signal @lib.pkg.pkg.pkg.obj : foo_t >>;
assert << variable @lib.pkg.pkg.obj : foo_t >>;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(external_constant_name
(package_pathname
library: (simple_name)
package: (simple_name)
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_signal_name
(package_pathname
library: (simple_name)
package: (simple_name)
package: (simple_name)
package: (simple_name)
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_variable_name
(package_pathname
library: (simple_name)
package: (simple_name)
package: (simple_name)
object: (simple_name))
(subtype_indication
(type_mark
(simple_name)))))))
================================================================================
Absolute pathname I
================================================================================
assert << constant .obj : foo_t >>;
assert << signal .foo.bar.obj : foo_t >>;
assert << variable .foo.obj : foo_t >>;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(external_constant_name
(absolute_pathname
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_signal_name
(absolute_pathname
(pathname_element
name_or_label: (simple_name))
(pathname_element
name_or_label: (simple_name))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_variable_name
(absolute_pathname
(pathname_element
name_or_label: (simple_name))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name)))))))
================================================================================
Absolute pathname II
================================================================================
assert << constant .foo(0).obj : bar >>;
assert << signal .foo(0).bar(0).obj : bar >>;
assert << variable .foo.bar(0).obj : bar >>;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(external_constant_name
(absolute_pathname
(pathname_element
(generate_statement_element
label: (simple_name)
specification: (expression
(integer_decimal))))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_signal_name
(absolute_pathname
(pathname_element
(generate_statement_element
label: (simple_name)
specification: (expression
(integer_decimal))))
(pathname_element
(generate_statement_element
label: (simple_name)
specification: (expression
(integer_decimal))))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_variable_name
(absolute_pathname
(pathname_element
name_or_label: (simple_name))
(pathname_element
(generate_statement_element
label: (simple_name)
specification: (expression
(integer_decimal))))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name)))))))
================================================================================
Relative pathname I
================================================================================
assert << constant obj : foo_t >>;
assert << signal foo.bar.obj : foo_t >>;
assert << variable foo.obj : foo_t >>;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(external_constant_name
(relative_pathname
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_signal_name
(relative_pathname
(pathname_element
name_or_label: (simple_name))
(pathname_element
name_or_label: (simple_name))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_variable_name
(relative_pathname
(pathname_element
name_or_label: (simple_name))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name)))))))
================================================================================
Relative pathname II
================================================================================
assert << constant obj : foo_t >>;
assert << signal ^.^.obj : foo_t >>;
assert << variable ^.obj : foo_t >>;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(external_constant_name
(relative_pathname
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_signal_name
(relative_pathname
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_variable_name
(relative_pathname
object: (simple_name))
(subtype_indication
(type_mark
(simple_name)))))))
================================================================================
Relative pathname III
================================================================================
assert << constant bar.obj : foo_t >>;
assert << signal ^.^.foobar.foo.bar.obj : foo_t >>;
assert << variable ^.foo.bar.obj : foo_t >>;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(external_constant_name
(relative_pathname
(pathname_element
name_or_label: (simple_name))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_signal_name
(relative_pathname
(pathname_element
name_or_label: (simple_name))
(pathname_element
name_or_label: (simple_name))
(pathname_element
name_or_label: (simple_name))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name))))))
(assertion_statement
(conditional_expression
(external_variable_name
(relative_pathname
(pathname_element
name_or_label: (simple_name))
(pathname_element
name_or_label: (simple_name))
object: (simple_name))
(subtype_indication
(type_mark
(simple_name)))))))

@ -0,0 +1,247 @@
===================================
Ambiguous name I
===================================
assert fun (obj);
---
(design_file
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))
===================================
Ambiguous name II
===================================
assert fun (bar, baz);
---
(design_file
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))
(expression
(simple_name)))))))
===================================
Predefine enumeration literal on actual I
===================================
assert fun ('+');
assert fun ("str");
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(positional_association_element
actual_part: (character_literal))))))
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(positional_association_element
actual_part: (string_literal)))))))
===================================
Predefine enumeration literal on actual II
===================================
assert fun (amb, '+');
assert fun (amb, "str");
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (character_literal))))))
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (string_literal)))))))
===================================
Named association element I
===================================
assert fun (foo => bar);
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(named_association_element
formal_part: (simple_name)
actual_part: (expression
(simple_name))))))))
===================================
Named association element II
===================================
assert fun (foo.bar => baz);
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(named_association_element
formal_part: (selected_name
prefix: (simple_name)
suffix: (simple_name))
actual_part: (expression
(simple_name))))))))
===================================
Mixed association list
===================================
assert fun (a, b => c);
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(named_association_element
formal_part: (simple_name)
actual_part: (expression
(simple_name))))))))
===================================
Open I
===================================
assert fun (open);
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(positional_association_element
actual_part: (open)))))))
===================================
Open II
===================================
assert fun (bar => open);
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(named_association_element
formal_part: (simple_name)
actual_part: (open)))))))
===================================
Open III
===================================
assert fun (fun (open));
---
(design_file
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(function_call
function: (simple_name)
(association_list
(positional_association_element
actual_part: (open))))))))))
===================================
Prefix - Operator symbol
===================================
assert "and" (foo, bar);
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (operator_symbol)
(association_list
(positional_association_element
actual_part: (expression
(simple_name)))
(positional_association_element
actual_part: (expression
(simple_name))))))))
===================================
Prefix - Attribute name
===================================
assert foo'bar (baz);
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (attribute_name
prefix: (simple_name)
designator: (simple_name))
(association_list
(positional_association_element
actual_part: (expression
(simple_name))))))))
===================================
Actual part I (Type conversion)
===================================
assert fun (t(param) => obj);
---
(design_file
(assertion_statement
(conditional_expression
(function_call
function: (simple_name)
(association_list
(named_association_element
formal_part: (ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))))
actual_part: (expression
(simple_name))))))))

@ -0,0 +1,117 @@
================================================================================
Ambiguous name I
================================================================================
assert arr (st);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))
================================================================================
Descending range
================================================================================
assert arr (h downto l);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(slice_name
prefix: (simple_name)
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name)))))))
================================================================================
Ascending range
================================================================================
assert arr (h to l);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(slice_name
prefix: (simple_name)
(ascending_range
low: (simple_expression
(simple_name))
high: (simple_expression
(simple_name)))))))
================================================================================
Attribute range
================================================================================
assert arr (st'range);
assert arr (st'reverse_range);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(slice_name
prefix: (simple_name)
(attribute_name
prefix: (simple_name)
designator: (predefined_designator)))))
(assertion_statement
(conditional_expression
(slice_name
prefix: (simple_name)
(attribute_name
prefix: (simple_name)
designator: (predefined_designator))))))
================================================================================
Prefix
================================================================================
assert amb (amb)(h downto l);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(slice_name
prefix: (ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))))
(descending_range
high: (simple_expression
(simple_name))
low: (simple_expression
(simple_name)))))))
================================================================================
Prefix - Selected name
================================================================================
assert MAC_CONFIG(i).TypeSwitch(0 to SWITCH_COUNT - 1);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(slice_name
prefix: (selected_name
prefix: (ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))))
suffix: (simple_name))
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(simple_expression
(simple_name)
(integer_decimal))))))))

@ -0,0 +1,71 @@
================================================================================
Minimal
================================================================================
library ieee;
entity e is
end entity;
--------------------------------------------------------------------------------
(design_file
(design_unit
(context_clause
(library_clause
(logical_name_list
(simple_name))))
(entity_declaration
(identifier))))
================================================================================
Logical name list
================================================================================
library work, ieee;
entity e is
end entity;
--------------------------------------------------------------------------------
(design_file
(design_unit
(context_clause
(library_clause
(logical_name_list
(simple_name)
(simple_name))))
(entity_declaration
(identifier))))
================================================================================
Context declaration - LRM
================================================================================
context project_context is
library project_lib;
use project_lib.project_defs.all;
library IP_lib;
context IP_lib.IP_context;
end context project_context;
--------------------------------------------------------------------------------
(design_file
(design_unit
(context_declaration
name: (identifier)
(context_clause
(library_clause
(logical_name_list
library: (simple_name)))
(use_clause
(selected_name
prefix: (selected_name
prefix: (simple_name)
suffix: (simple_name))
suffix: (all)))
(library_clause
(logical_name_list
library: (simple_name)))
(context_reference
(context_list
(selected_name
prefix: (simple_name)
suffix: (simple_name)))))
at_end: (simple_name))))

@ -0,0 +1,140 @@
====================================
Constant Parameter Specification I
====================================
sequence s (const c) is {c};
---
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification)
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Boolean
(simple_name)))))
====================================
Constant Parameter Specification II
====================================
sequence s (boolean b) is {b};
---
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Boolean
(simple_name)))))
====================================
Constant Parameter Specification III
====================================
sequence s (const boolean b) is {b};
---
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Boolean
(simple_name)))))
====================================
Constant Parameter Specification IV
====================================
sequence s (hdltype t o) is {o};
---
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_HDL_Type
(subtype_indication
(type_mark
(simple_name)))))
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Boolean
(simple_name)))))
====================================
Constant Parameter Specification V
====================================
sequence s (const hdltype t o) is {o};
---
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_HDL_Type
(subtype_indication
(type_mark
(simple_name)))))
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Boolean
(simple_name)))))
====================================
Temporal Parameter Specification I
====================================
sequence s1 (sequence s2) is s2;
---
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Temporal_Parameter_Specification)
(PSL_Identifier)))
(PSL_Sequence_Instance
(PSL_Identifier))))
====================================
Formal parameter list
====================================
property s1 (property p; sequence s; const k) is p(s,k);
---
(design_file
(PSL_Property_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Temporal_Parameter_Specification)
(PSL_Identifier))
(PSL_Formal_Parameter
(PSL_Temporal_Parameter_Specification)
(PSL_Identifier))
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification)
(PSL_Identifier)))
(PSL_Property_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))))))

@ -0,0 +1,751 @@
================================================================================
PSL LRM 1.3.1
================================================================================
assert always {req; ack_n; not cancel} |=> (ena or enb);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))
(PSL_Boolean
(factor
(simple_name)))))
Property: (PSL_Boolean
(parenthesized_expression
(logical_expression
(simple_name)
(simple_name))))))))
================================================================================
PSL LRM 1.3.2.1 Simulation (Property 1)
================================================================================
assert always (req -> next not req);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(factor
(simple_name)))))))))
================================================================================
PSL LRM 1.3.2.1 Simulation (Property 2)
================================================================================
assert always (a -> next[3] (b));
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Extended_Ocurrence_FL_Property
(PSL_Count
(PSL_Number
(integer_decimal)))
Property: (PSL_Boolean
(simple_name))))))))
================================================================================
PSL LRM 1.3.2.1 Simulation (Property 3)
================================================================================
assert always ((a and next[3] (b)) -> c);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Logical_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Extended_Ocurrence_FL_Property
(PSL_Count
(PSL_Number
(integer_decimal)))
Property: (PSL_Boolean
(simple_name)))))
(PSL_Boolean
(simple_name)))))))
================================================================================
PSL LRM 6.2.3 Replicated properties I
================================================================================
assert forall i in boolean: f(i);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(boolean)))
Property: (PSL_Property_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name))))))))
================================================================================
PSL LRM 6.2.3 Replicated properties II
================================================================================
assert forall i in {j to k} : f(i);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(ascending_range
low: (simple_expression
(simple_name))
high: (simple_expression
(simple_name)))))
Property: (PSL_Property_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name))))))))
================================================================================
PSL LRM 6.2.3 Replicated properties III
================================================================================
assert forall i (0 to 1) in boolean : f(i);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Index_Range
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))
(PSL_Value_Set
(boolean)))
Property: (PSL_Property_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name))))))))
================================================================================
PSL LRM 6.2.3 Replicated properties IV
================================================================================
assert forall i (0 to 2) in {4,5} : f(i);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Index_Range
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))
(PSL_Value_Set
(PSL_Any_Type
(integer_decimal))
(PSL_Any_Type
(integer_decimal))))
Property: (PSL_Property_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name))))))))
================================================================================
PSL LRM 6.2.3 Replicated properties V
================================================================================
assert forall i(0 to 3) in boolean:
request and (data_in = i) -> next(data_out = i);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Index_Range
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))
(PSL_Value_Set
(boolean)))
Property: (PSL_Expression
(PSL_Boolean
(logical_expression
(simple_name)
(parenthesized_expression
(relation
(simple_name)
(simple_name)))))
(PSL_Built_In_Function_Call
(PSL_Any_Type
(relation
(simple_name)
(simple_name))))))))
================================================================================
PSL LRM 6.2.3 Replicated properties VI
================================================================================
assert forall i in boolean:
forall j in {0 to 7}:
forall k in {0 to 3}:
f(i,j,k);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(boolean)))
Property: (PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))
Property: (PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))
Property: (PSL_Property_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name))))))))))
================================================================================
PSL LRM 6.2.3 Replicated properties VII
================================================================================
assert forall j in {0 to 7}:
forall k in {0 to j}:
f(j);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))
Property: (PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(simple_name)))))
Property: (PSL_Property_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))))))))
================================================================================
PSL LRM 6.3.1 PSL formal parameter type classes
================================================================================
sequence s (boolean b0, b1) is {b0 = b1};
--------------------------------------------------------------------------------
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Boolean
(relation
(simple_name)
(simple_name))))))
================================================================================
PSL LRM 6.3.2 HDL formal parameter types I
================================================================================
sequence color_is_red (hdltype COLOR c) is {c = RED};
--------------------------------------------------------------------------------
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_HDL_Type
(subtype_indication
(type_mark
(simple_name)))))
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Boolean
(relation
(simple_name)
(simple_name))))))
================================================================================
PSL LRM 6.3.2 HDL formal parameter types II
================================================================================
sequence slope_is_1 (hdltype COORDINATE_RECORD c) is {(c.x / c.y) = 1};
--------------------------------------------------------------------------------
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_HDL_Type
(subtype_indication
(type_mark
(simple_name)))))
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Boolean
(relation
(parenthesized_expression
(term
(selected_name
prefix: (simple_name)
suffix: (simple_name))
(selected_name
prefix: (simple_name)
suffix: (simple_name))))
(integer_decimal))))))
================================================================================
PSL LRM 6.3.2.1 - Sequence declaration I
================================================================================
sequence BusArb (boolean br, bg; const n) is
{ br; (br and not bg)[*0 to n]; br and bg };
--------------------------------------------------------------------------------
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)
(PSL_Identifier))
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification)
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Boolean
(simple_name))
(PSL_Repeated_SERE
(PSL_Boolean
(parenthesized_expression
(logical_expression
(simple_name)
(factor
(simple_name)))))
(PSL_Count
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(simple_name)))))
(PSL_Boolean
(logical_expression
(simple_name)
(simple_name)))))))
================================================================================
PSL LRM 6.3.2.1 - Sequence declaration II
================================================================================
sequence ReadCycle (sequence ba; boolean bb, ar, dr) is
{ ba; {bb[*]} && {ar[->]; dr[->]}; not bb };
--------------------------------------------------------------------------------
(design_file
(PSL_Sequence_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Temporal_Parameter_Specification)
(PSL_Identifier))
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)
(PSL_Identifier)
(PSL_Identifier)))
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Boolean
(simple_name))
(PSL_Compound_SERE
(PSL_Braced_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count)))
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count))
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count)))))
(PSL_Boolean
(factor
(simple_name)))))))
================================================================================
PSL LRM 6.3.2.2 - Property declaration I
================================================================================
property ResultAfterN
(boolean start; property result; const n; boolean stop) is
always ((start -> next[n] (result)) @ (rising_edge(clk)) async_abort stop);
--------------------------------------------------------------------------------
(design_file
(PSL_Property_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier))
(PSL_Formal_Parameter
(PSL_Temporal_Parameter_Specification)
(PSL_Identifier))
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification)
(PSL_Identifier))
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)))
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Termination_FL_Property
(PSL_Clocked_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Extended_Ocurrence_FL_Property
(PSL_Count
(PSL_Number
(simple_name)))
Property: (PSL_Boolean
(simple_name)))))
(conditional_expression
(parenthesized_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))
(PSL_Boolean
(simple_name)))))))
================================================================================
PSL LRM 6.3.2.2 - Property declaration II
================================================================================
property ResultAfterN
(boolean start, stop; property result; const n) is
always ((start -> next[n] (result)) @ (rising_edge(clk))
async_abort stop);
--------------------------------------------------------------------------------
(design_file
(PSL_Property_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)
(PSL_Identifier))
(PSL_Formal_Parameter
(PSL_Temporal_Parameter_Specification)
(PSL_Identifier))
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification)
(PSL_Identifier)))
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Termination_FL_Property
(PSL_Clocked_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Extended_Ocurrence_FL_Property
(PSL_Count
(PSL_Number
(simple_name)))
Property: (PSL_Boolean
(simple_name)))))
(conditional_expression
(parenthesized_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))
(PSL_Boolean
(simple_name)))))))
================================================================================
PSL LRM 6.3.3.1 - Sequence instantiation I
================================================================================
restrict BusArb (breq, back, 3);
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Sequence_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(integer_decimal)))))))
================================================================================
PSL LRM 6.3.3.1 - Sequence instantiation II
================================================================================
restrict { breq; (breq and not back)[*0 to 3]; breq and back };
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Boolean
(simple_name))
(PSL_Repeated_SERE
(PSL_Boolean
(parenthesized_expression
(logical_expression
(simple_name)
(factor
(simple_name)))))
(PSL_Count
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))
(PSL_Boolean
(logical_expression
(simple_name)
(simple_name)))))))
================================================================================
PSL LRM 6.3.3.1 - Sequence instantiation III
================================================================================
restrict ReadCycle(BusArb(breq, back, 5), breq, ardy, drdy);
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Sequence_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))
(expression
(simple_name))
(expression
(integer_decimal))))))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))))))
================================================================================
PSL LRM 6.3.3.1 - Sequence instantiation IV
================================================================================
restrict { { breq; (breq and not back)[*0 to 5]; breq and back };
{breq[*]} && {ardy[->]}; drdy[->]; not breq};
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Boolean
(simple_name))
(PSL_Repeated_SERE
(PSL_Boolean
(parenthesized_expression
(logical_expression
(simple_name)
(factor
(simple_name)))))
(PSL_Count
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))
(PSL_Boolean
(logical_expression
(simple_name)
(simple_name)))))
(PSL_Compound_SERE
(PSL_Braced_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count)))
(PSL_Braced_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count))))
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count))
(PSL_Boolean
(factor
(simple_name)))))))
================================================================================
PSL LRM 6.3.3.2 - Property instantiation I
================================================================================
assert ResultAfterN (write_req, eventually! ack, 3, cancel);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Ambiguous_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name))))
(PSL_Actual_Parameter
(PSL_Any_Type
(integer_decimal)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))))))
================================================================================
PSL LRM 6.3.3.2 - Property instantiation II
================================================================================
assert always ((write_req -> next[3] (eventually! ack))
@ (rising_edge(clk)) async_abort cancel);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Termination_FL_Property
(PSL_Clocked_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Extended_Ocurrence_FL_Property
(PSL_Count
(PSL_Number
(integer_decimal)))
Property: (PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name))))))
(conditional_expression
(parenthesized_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))
(PSL_Boolean
(simple_name)))))))

@ -0,0 +1,575 @@
================================================================================
Property replicator
================================================================================
assert forall p in boolean : p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(boolean)))
Property: (PSL_Property_Instance
(PSL_Identifier)))))
================================================================================
Property replicator - Index Range I
================================================================================
assert forall p (0 to 1) in boolean : p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Index_Range
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))
(PSL_Value_Set
(boolean)))
Property: (PSL_Property_Instance
(PSL_Identifier)))))
================================================================================
Replicator - Index Range II
================================================================================
assert forall p (1 downto 0) in boolean : p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Index_Range
(descending_range
high: (simple_expression
(integer_decimal))
low: (simple_expression
(integer_decimal))))
(PSL_Value_Set
(boolean)))
Property: (PSL_Property_Instance
(PSL_Identifier)))))
================================================================================
Replicator - Index Range - VHDL Range III
================================================================================
assert forall p (foo'range) in boolean : p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Index_Range
(attribute_name
prefix: (simple_name)
designator: (predefined_designator)))
(PSL_Value_Set
(boolean)))
Property: (PSL_Property_Instance
(PSL_Identifier)))))
================================================================================
Replicator - Value Set I
================================================================================
assert forall p in {0 to 1} : p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))
Property: (PSL_Property_Instance
(PSL_Identifier)))))
================================================================================
Replicator - Value Set II
================================================================================
assert forall p in {0 to 1, 0 to 1} : p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))
Property: (PSL_Property_Instance
(PSL_Identifier)))))
================================================================================
Replicator - Value Set - Value
================================================================================
assert forall p in {val} : p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Property_Replicator
(PSL_Parameter_Specification
(PSL_Identifier)
(PSL_Value_Set
(PSL_Any_Type
(simple_name))))
Property: (PSL_Property_Instance
(PSL_Identifier)))))
================================================================================
Clock property
================================================================================
assert a @ clk;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Clocked_FL_Property
(PSL_Boolean
(simple_name))
(conditional_expression
(simple_name)))))
================================================================================
Termination property
================================================================================
assert a abort b;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Termination_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name)))))
================================================================================
Logical expression (binary) property
================================================================================
assert (a->b) and b;
assert a or (a->b);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Logical_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Logical_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Parenthesized_FL_Property
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name)))))))
================================================================================
Implication property
================================================================================
assert (a->b) -> b;
assert a <-> (a->b);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Implication_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Parenthesized_FL_Property
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name)))))))
================================================================================
Logical expression (unary) property
================================================================================
assert not (a->b);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Factor_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name)))))))
================================================================================
Logical expression (combined) property
================================================================================
assert not (a->b) and b;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Logical_FL_Property
(PSL_Factor_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name)))))
(PSL_Boolean
(simple_name)))))
================================================================================
Invariance property
================================================================================
assert always p;
assert never p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Boolean
(simple_name)))))
================================================================================
Ocurrence property
================================================================================
assert next p;
assert next! p;
assert eventually! p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name)))))
================================================================================
Bounding property
================================================================================
assert p until! p;
assert p until p;
assert p until!_ p;
assert p until_ p;
assert p before! p;
assert p before p;
assert p before!_ p;
assert p before p;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name)))))
================================================================================
Extended ocurrence property I
================================================================================
assert next (p);
assert next! (p);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Built_In_Function_Call
(PSL_Any_Type
(simple_name))))
(PSL_Assert_Directive
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(parenthesized_expression
(simple_name))))))
================================================================================
Extended ocurrence property II
================================================================================
assert next [1] (p);
assert next! [2] (p);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
(PSL_Count
(PSL_Number
(integer_decimal)))
Property: (PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
(PSL_Count
(PSL_Number
(integer_decimal)))
Property: (PSL_Boolean
(simple_name)))))
================================================================================
Extended ocurrence (all) property I
================================================================================
assert next_a [0 to 1] (p);
assert next_a! [0 to 1] (p);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
(PSL_Count
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))
Property: (PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
(PSL_Count
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))
Property: (PSL_Boolean
(simple_name)))))
================================================================================
Extended ocurrence event property I
================================================================================
assert next_event (b) (p);
assert next_event! (b) (p);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
Boolean: (PSL_Boolean
(simple_name))
Property: (PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
Boolean: (PSL_Boolean
(simple_name))
Property: (PSL_Boolean
(simple_name)))))
================================================================================
Extended ocurrence event property II
================================================================================
assert next_event (b) [1] (p);
assert next_event! (b) [1] (p);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
Boolean: (PSL_Boolean
(simple_name))
(PSL_Count
(PSL_Number
(integer_decimal)))
Property: (PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
Boolean: (PSL_Boolean
(simple_name))
(PSL_Count
(PSL_Number
(integer_decimal)))
Property: (PSL_Boolean
(simple_name)))))
================================================================================
Sequence Instantiation I (Ambiguos)
================================================================================
assert p;
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(simple_name))))
================================================================================
Property Instantiation II (Ambiguos)
================================================================================
assert p(a);
--------------------------------------------------------------------------------
(design_file
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))
================================================================================
Property Instantiation III
================================================================================
assert p (a -> b, a -> b);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Ambiguous_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Actual_Parameter
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))))))
================================================================================
Property Instantiation IV
================================================================================
assert ResultAfterN (eventually! ack);
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Ambiguous_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name))))))))
================================================================================
Clocked property
================================================================================
assert (c and next! (a until! b)@clk1)@clk2 ;
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Clocked_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Logical_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Ocurrence_FL_Property
(PSL_Clocked_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(conditional_expression
(simple_name))))))
(conditional_expression
(simple_name)))))

@ -0,0 +1,154 @@
================================================================================
Repeated sequence I
================================================================================
restrict {a[*2]};
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Braced_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count
(PSL_Number
(integer_decimal)))))))
================================================================================
Repeated sequence II
================================================================================
restrict {a[+]};
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Braced_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count)))))
================================================================================
Repeated sequence III
================================================================================
restrict {a[*]};
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Braced_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count)))))
================================================================================
Repeated sequence IV
================================================================================
restrict {[*]};
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Braced_SERE
(PSL_Repeated_SERE
(PSL_Count)))))
================================================================================
Repeated sequence V
================================================================================
restrict {a[=2]};
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Braced_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count
(PSL_Number
(integer_decimal)))))))
================================================================================
Repeated sequence VI
================================================================================
restrict {a[*1 to 3]};
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Braced_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal))))))))
================================================================================
Sequence Instantiation - Minimal
================================================================================
restrict s;
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Sequence_Instance
(PSL_Identifier))))
================================================================================
Sequence Instantiation - LRM I
================================================================================
restrict BusArb(breq, back, 3);
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Sequence_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(integer_decimal)))))))
================================================================================
Sequence Instantiation - LRM II
================================================================================
restrict ReadCycle(BusArb(breq, back, 5), breq, ardy, drdy);
--------------------------------------------------------------------------------
(design_file
(PSL_Restrict_Directive
(PSL_Sequence_Instance
(PSL_Identifier)
(PSL_Actual_Parameter_List
(PSL_Actual_Parameter
(PSL_Any_Type
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))
(expression
(simple_name))
(expression
(integer_decimal))))))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))
(PSL_Actual_Parameter
(PSL_Any_Type
(simple_name)))))))

@ -0,0 +1,356 @@
================================================================================
SERE_0_a
================================================================================
assert always {a} |=> {b; b; b; b; c};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_1_a
================================================================================
assert always {a} |=> {b[*4]; c};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count
(PSL_Number
(integer_decimal))))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_2_a
================================================================================
assert always {a} |=> {b[*3 to 5]; c};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_3_a
================================================================================
assert always {a} |=> {b[*]; c};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_4_a
================================================================================
assert always {a} |=> {b[+]; c};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_5_a
================================================================================
assert always {d} |=> {e[*]; f};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_6_a
================================================================================
assert always {d} |=> {e[+]; f};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_7_a
================================================================================
assert always {g} |=> {h[*3]; i};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count
(PSL_Number
(integer_decimal))))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_8_a
================================================================================
assert always {g} |=> {h[*2 to 4]; i};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(integer_decimal)))))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_9_a
================================================================================
assert always {g} |=> {h[*]; i};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_10_a
================================================================================
assert always {g} |=> {h[+]; i};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Boolean
(simple_name))
(PSL_Count))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_11_a
================================================================================
assert always {g} |=> {[*6]; i};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Count
(PSL_Number
(integer_decimal))))
(PSL_Boolean
(simple_name)))))))))
================================================================================
SERE_12_a
================================================================================
assert always {g} |=> {[*6]; i; not i[*1 to inf]};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Count
(PSL_Number
(integer_decimal))))
(PSL_Boolean
(simple_name))
(PSL_Repeated_SERE
(PSL_Boolean
(factor
(simple_name)))
(PSL_Count
(ascending_range
low: (simple_expression
(integer_decimal))
high: (simple_expression
(simple_name))))))))))))
================================================================================
SERE_13_a
================================================================================
assert always {g} |=> {{h; not h}[*3]; i};
--------------------------------------------------------------------------------
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Suffix_Implication_FL_Property
Sequence: (PSL_Braced_SERE
(PSL_Boolean
(simple_name)))
Property: (PSL_Sequential_FL_Property
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Repeated_SERE
(PSL_Braced_SERE
(PSL_Simple_SERE
(PSL_Boolean
(simple_name))
(PSL_Boolean
(factor
(simple_name)))))
(PSL_Count
(PSL_Number
(integer_decimal))))
(PSL_Boolean
(simple_name)))))))))

@ -0,0 +1,267 @@
================================
Assertion Statement
================================
assert a and b;
assert (a and b);
---
(design_file
(assertion_statement
(conditional_expression
(logical_expression
(simple_name)
(simple_name))))
(assertion_statement
(conditional_expression
(parenthesized_expression
(logical_expression
(simple_name)
(simple_name))))))
================================
Assert Directive - Implication
================================
assert a -> b;
assert (a -> b);
---
(design_file
(PSL_Assert_Directive
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Parenthesized_FL_Property
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))))
================================
Function call - Next
================================
assert next(x);
assert foo(x);
foo <= next(x);
---
(design_file
(PSL_Assert_Directive
(PSL_Built_In_Function_Call
(PSL_Any_Type
(simple_name))))
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))))
================================
Function call - Sequence I
================================
assert nondet({x});
assert nondet({x,y});
---
(design_file
(PSL_Assert_Directive
(PSL_Built_In_Function_Call
(PSL_Value_Set
(PSL_Any_Type
(simple_name)))))
(PSL_Assert_Directive
(PSL_Built_In_Function_Call
(PSL_Value_Set
(PSL_Any_Type
(simple_name))
(PSL_Any_Type
(simple_name))))))
================================
Function call - Sequence II
================================
assert ended({x});
---
(design_file
(PSL_Assert_Directive
(PSL_Built_In_Function_Call
(PSL_Braced_SERE
(PSL_Boolean
(simple_name))))))
================================
Next conflict I
================================
assert next (a);
assert next (a -> b);
assert next (x) (y);
---
(design_file
(PSL_Assert_Directive
(PSL_Built_In_Function_Call
(PSL_Any_Type
(simple_name))))
(PSL_Assert_Directive
(PSL_Built_In_Function_Call
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name)))))
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
Boolean: (PSL_Boolean
(simple_name))
Property: (PSL_Boolean
(simple_name)))))
================================
Next not-conflict
================================
assert next! (a);
assert next! (a -> b);
assert next! (x) (y);
---
(design_file
(PSL_Assert_Directive
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(parenthesized_expression
(simple_name)))))
(PSL_Assert_Directive
(PSL_Ocurrence_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))))
(PSL_Assert_Directive
(PSL_Extended_Ocurrence_FL_Property
Boolean: (PSL_Boolean
(simple_name))
Property: (PSL_Boolean
(simple_name)))))
================================
Next conflict II
================================
assert next (a before b);
---
(design_file
(PSL_Assert_Directive
(PSL_Ocurrence_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name)))))))
================================
PSL Expression
================================
assert c -> x;
assert c -> (x);
assert c -> next(x);
---
(design_file
(PSL_Assert_Directive
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))
(PSL_Assert_Directive
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Boolean
(parenthesized_expression
(simple_name)))))
(PSL_Assert_Directive
(PSL_Expression
(PSL_Boolean
(simple_name))
(PSL_Built_In_Function_Call
(PSL_Any_Type
(simple_name))))))
================================
Implication operator
================================
assert c -> next x;
assert c -> (next x);
assert c -> (next (x));
---
(design_file
(PSL_Assert_Directive
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name)))))
(PSL_Assert_Directive
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Parenthesized_FL_Property
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name))))))
(PSL_Assert_Directive
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Parenthesized_FL_Property
(PSL_Built_In_Function_Call
(PSL_Any_Type
(simple_name)))))))
================================
Test
================================
assert always (e -> (f or next (f before e)));
---
(design_file
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Parenthesized_FL_Property
(PSL_Logical_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Ocurrence_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Bounding_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Boolean
(simple_name))))))))))))

@ -0,0 +1,435 @@
================================================================================
LRM 7.2.1 - I
================================================================================
vunit ex1a(top_block.i1.i2) {
A1: assert never (ena and enb);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name)
instance: (simple_name)
instance: (simple_name))
(PSL_Assert_Directive
(label
(identifier))
(PSL_Invariant_FL_Property
(PSL_Boolean
(parenthesized_expression
(logical_expression
(simple_name)
(simple_name))))))))))
================================================================================
LRM 7.2.1 - II
================================================================================
vunit ex2a(mod1) {
assert never (ena and enb);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name))
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Boolean
(parenthesized_expression
(logical_expression
(simple_name)
(simple_name))))))))))
================================================================================
LRM 7.2.1 - III
================================================================================
vunit ex2b(top_block.i1) {
assert never (i2.ena and i2.enb);
assert never (i3.ena and i3.enb);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name)
instance: (simple_name))
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Boolean
(parenthesized_expression
(logical_expression
(selected_name
prefix: (simple_name)
suffix: (simple_name))
(selected_name
prefix: (simple_name)
suffix: (simple_name)))))))
(PSL_Assert_Directive
(PSL_Invariant_FL_Property
(PSL_Boolean
(parenthesized_expression
(logical_expression
(selected_name
prefix: (simple_name)
suffix: (simple_name))
(selected_name
prefix: (simple_name)
suffix: (simple_name)))))))))))
================================================================================
LRM 7.2.1 - IV
================================================================================
vunit ex3 {
A3: assert never (ena and enb);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Assert_Directive
(label
(identifier))
(PSL_Invariant_FL_Property
(PSL_Boolean
(parenthesized_expression
(logical_expression
(simple_name)
(simple_name))))))))))
================================================================================
LRM 7.2.1 - V
================================================================================
vunit ex4 {
property mutex (boolean b1, b2) is never (b1 and b2);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Property_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)
(PSL_Identifier)))
(PSL_Invariant_FL_Property
(PSL_Boolean
(parenthesized_expression
(logical_expression
(simple_name)
(simple_name))))))))))
================================================================================
LRM 7.2.2 - I
================================================================================
vmode Common {
property mutex (boolean b1, b2) is never b1 and b2 ;
property one_hot (boolean b1, b2) is always ((b1 and b2) or (b2 and not b1));
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VMode
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Property_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)
(PSL_Identifier)))
(PSL_Invariant_FL_Property
(PSL_Boolean
(logical_expression
(simple_name)
(simple_name)))))
(PSL_Property_Declaration
(PSL_Identifier)
(PSL_Formal_Parameter_List
(PSL_Formal_Parameter
(PSL_Constant_Parameter_Specification
(PSL_Type_Class))
(PSL_Identifier)
(PSL_Identifier)))
(PSL_Invariant_FL_Property
(PSL_Boolean
(parenthesized_expression
(logical_expression
(parenthesized_expression
(logical_expression
(simple_name)
(simple_name)))
(parenthesized_expression
(logical_expression
(simple_name)
(factor
(simple_name)))))))))))))
================================================================================
LRM 7.2.2 - II
================================================================================
vmode Amode (blockA) {
inherit Common;
assume mutex(Aout1, Aout2);
}
vmode Bmode (blockB) {
inherit Common;
assume one_hot(Bout1, Bout2);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VMode
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name))
(PSL_Inherit_Spec
(simple_name))
(PSL_Assume_Directive
(PSL_Boolean
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))
(expression
(simple_name)))))))))
(design_unit
(PSL_VMode
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name))
(PSL_Inherit_Spec
(simple_name))
(PSL_Assume_Directive
(PSL_Boolean
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))
(expression
(simple_name))))))))))
================================================================================
LRM 7.2.2 - III
================================================================================
vunit Aprops (blockA) {
inherit Common, Bmode;
assert mutex(Aout1, Aout2);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name))
(PSL_Inherit_Spec
(simple_name)
(simple_name))
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))
(expression
(simple_name))))))))))
================================================================================
LRM 7.2.2 - IV
================================================================================
vunit Bprops (blockB) {
inherit Common, Amode;
assert one_hot(Bout1, Bout2);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name))
(PSL_Inherit_Spec
(simple_name)
(simple_name))
(assertion_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name))
(expression
(simple_name))))))))))
================================================================================
LRM 7.2.3 - I
================================================================================
vunit ex5a(top_block.i1) {
signal reqa, temp : boolean;
A5a: assert always (reqa -> next temp);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name)
instance: (simple_name))
(signal_declaration
(identifier_list
(identifier)
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(PSL_Assert_Directive
(label
(identifier))
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name)))))))))))
================================================================================
LRM 7.2.3 - II
================================================================================
vunit ex5b(top_block.i1) {
signal temp : boolean;
temp <= ack1 or ack2;
A5b: assert always (reqa -> next temp);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name)
instance: (simple_name))
(signal_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(logical_expression
(simple_name)
(simple_name))))))
(PSL_Assert_Directive
(label
(identifier))
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Boolean
(simple_name))
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name)))))))))))
================================================================================
LRM 7.2.3 - III
================================================================================
vunit ex5d(top_block.i1) {
signal reqa : boolean;
reqa <= nondet((0,1));
A5c: assert always ((reqa or reqb) -> next temp);
}
--------------------------------------------------------------------------------
(design_file
(design_unit
(PSL_VUnit
(PSL_Identifier)
(PSL_Verification_Unit_Body
(PSL_Hierarchical_HDL_Name
entity: (simple_name)
instance: (simple_name))
(signal_declaration
(identifier_list
(identifier))
(subtype_indication
(type_mark
(simple_name))))
(simple_concurrent_signal_assignment
target: (simple_name)
(waveforms
(waveform_element
(expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(aggregate
(positional_element_association
(expression
(integer_decimal)))
(positional_element_association
(expression
(integer_decimal)))))))))))
(PSL_Assert_Directive
(label
(identifier))
(PSL_Invariant_FL_Property
(PSL_Parenthesized_FL_Property
(PSL_Implication_FL_Property
(PSL_Boolean
(parenthesized_expression
(logical_expression
(simple_name)
(simple_name))))
(PSL_Ocurrence_FL_Property
(PSL_Boolean
(simple_name)))))))))))

@ -0,0 +1,109 @@
===========================
Ordinary case statement
===========================
case expr is
end case;
L1:
case expr is
end case;
L2:
case expr is
end case L2;
---
(design_file
(case_statement
(expression
(simple_name)))
(case_statement
(label
(identifier))
(expression
(simple_name)))
(case_statement
(label
(identifier))
(expression
(simple_name))
at_end: (simple_name)))
===========================
Matching case statement
===========================
case? expr is
end case?;
L1:
case? expr is
end case?;
L2:
case? expr is
end case? L2;
---
(design_file
(case_statement
(expression
(simple_name)))
(case_statement
(label
(identifier))
(expression
(simple_name)))
(case_statement
(label
(identifier))
(expression
(simple_name))
at_end: (simple_name)))
===================================
Case statement alternatives
===================================
case expr is
when a =>
when b | c =>
when others =>
end case;
---
(design_file
(case_statement
(expression
(simple_name))
(case_statement_alternative
(choices
(simple_expression
(simple_name))))
(case_statement_alternative
(choices
(simple_expression
(simple_name))
(simple_expression
(simple_name))))
(case_statement_alternative
(choices
(others)))))
===================================
Sequence os statements
===================================
case expr is
when a =>
null;
end case;
---
(design_file
(case_statement
(expression
(simple_name))
(case_statement_alternative
(choices
(simple_expression
(simple_name)))
(sequence_of_statements
(null_statement)))))

@ -0,0 +1,103 @@
================================
Minimal
================================
if true then
end if;
L2:
if true then
end if;
L3:
if true then
end if L3;
---
(design_file
(if_statement
(if
(conditional_expression
(simple_name))))
(if_statement
(label
(identifier))
(if
(conditional_expression
(simple_name))))
(if_statement
(label
(identifier))
(if
(conditional_expression
(simple_name)))
at_end: (simple_name)))
================================
Elsif
================================
if true then
elsif true then
end if;
---
(design_file
(if_statement
(if
(conditional_expression
(simple_name)))
(elsif
(conditional_expression
(simple_name)))))
================================
Else
================================
if true then
elsif true then
else
end if;
---
(design_file
(if_statement
(if
(conditional_expression
(simple_name)))
(elsif
(conditional_expression
(simple_name)))
(else)))
================================
Sequence os statements
================================
if true then
null;
elsif true then
null;
null;
else
null;
null;
null;
end if;
---
(design_file
(if_statement
(if
(conditional_expression
(simple_name))
(sequence_of_statements
(null_statement)))
(elsif
(conditional_expression
(simple_name))
(sequence_of_statements
(null_statement)
(null_statement)))
(else
(sequence_of_statements
(null_statement)
(null_statement)
(null_statement)))))

@ -0,0 +1,116 @@
===================================
Minmal
===================================
loop
end loop;
L1:
loop
end loop;
L2:
loop
end loop L2;
---
(design_file
(loop_statement)
(loop_statement
(label (identifier)))
(loop_statement
(label (identifier))
at_end: (simple_name)))
===================================
Iteration scheme - While
===================================
while cond
loop
end loop;
---
(design_file
(loop_statement
(while_loop
(conditional_expression
(simple_name)))))
===================================
Iteration scheme - For loop
===================================
for c in st
loop
end loop;
---
(design_file
(loop_statement
(for_loop
(parameter_specification
(identifier)
(subtype_indication
(type_mark
(simple_name)))))))
===================================
Next I
===================================
loop
next;
end loop;
---
(design_file
(loop_statement
(sequence_of_statements
(next_statement))))
===================================
Next II
===================================
for c in st
loop
next when cond;
end loop;
---
(design_file
(loop_statement
(for_loop
(parameter_specification
(identifier)
(subtype_indication
(type_mark
(simple_name)))))
(sequence_of_statements
(next_statement
(conditional_expression
(simple_name))))))
===================================
Exit I
===================================
loop
exit;
end loop;
---
(design_file
(loop_statement
(sequence_of_statements
(exit_statement))))
===================================
Exit II
===================================
loop
exit when e;
end loop;
---
(design_file
(loop_statement
(sequence_of_statements
(exit_statement
(conditional_expression
(simple_name))))))

@ -0,0 +1,30 @@
================================
Report - Minimal
================================
report "str";
L1: report "str";
---
(design_file
(report_statement
(string_expression
(string_literal)))
(report_statement
(label
(identifier))
(string_expression
(string_literal))))
================================
Report - Severity
================================
report K_MSG severity note;
---
(design_file
(report_statement
(string_expression
(simple_name))
(severity_expression
(simple_name))))

@ -0,0 +1,71 @@
================================================================================
Wait - Minimal
================================================================================
wait;
L: wait;
--------------------------------------------------------------------------------
(design_file
(wait_statement)
(wait_statement
(label
(identifier))))
================================================================================
Wait - Sensitivity clause
================================================================================
wait on a;
--------------------------------------------------------------------------------
(design_file
(wait_statement
(sensitivity_list
(simple_name))))
================================================================================
Wait - Conditon clause
================================================================================
wait until rising_edge(clk);
--------------------------------------------------------------------------------
(design_file
(wait_statement
(conditional_expression
(ambiguous_name
prefix: (simple_name)
(expression_list
(expression
(simple_name)))))))
================================================================================
Wait - Timeout clause
================================================================================
wait for 10 ns;
--------------------------------------------------------------------------------
(design_file
(wait_statement
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))
================================================================================
Wait - All clauses
================================================================================
L1: wait on foo, bar until cond for 1 ms;
--------------------------------------------------------------------------------
(design_file
(wait_statement
(label
(identifier))
(sensitivity_list
(simple_name)
(simple_name))
(conditional_expression
(simple_name))
(time_expression
(physical_literal
(integer_decimal)
unit: (simple_name)))))

@ -0,0 +1,4 @@
architecture a of e is
begin
end architecture b;
-- ^ error.misspeling.name

@ -0,0 +1,86 @@
architecture a of e is
variable s : t;
-- ^ error.illegal.declaration
procedure p;
function f return t;
procedure p is
begin
end procedure;
function f return t is
begin
end function;
procedure p2 is new up;
function f2 is new uf;
package pkg is
end;
package body pkg is
end;
package pkg2 is new upkg;
type t is range 0 to 7;
subtype st is t;
constant k : t;
signal s : t;
shared variable s : t;
file f : t;
alias a is k;
component c is
end component;
attribute a of e : entity is x;
attribute a : t;
for l : c
use open;
disconnect s : t after 10 ns;
use foo.bar;
group G1 : E (L2);
group g is (signal);
assert c;
assume c;
assume_guarantee c;
restrict c;
restrict_guarantee c;
cover c;
fairness c;
strong fairness c,c;
property p is (a -> b);
sequence s is {c};
default clock is rising_edge(clk);
begin
end;

@ -0,0 +1,15 @@
type foo_t is array (resolve_f foobar_t) of bar_t;
-- ^ error.unexpected.resolution_function
for k in foo_f bar_t
-- ^ error.unexpected.resolution_function
loop
end loop;
type foo_t is array (3 downto 0) of foo_t;
-- ^ error.repeated.type
type foo_t is array (integer range <>) of foo_t;
-- ^ error.repeated.type

@ -0,0 +1,3 @@
entity ent is
end entity foo;
-- ^ error.misspeling.name

@ -0,0 +1,86 @@
entity e is
variable s : t;
-- ^ error.illegal.declaration
component c is
-- ^ error.illegal.declaration
end component;
for l : c
-- ^ error.illegal.declaration
use open;
procedure p;
function f return t;
procedure p is
begin
end procedure;
function f return t is
begin
end function;
procedure p2 is new up;
function f2 is new uf;
package pkg is
end;
package body pkg is
end;
package pkg2 is new upkg;
type t is range 0 to 7;
subtype st is t;
constant k : t;
signal s : t;
shared variable s : t;
file f : t;
alias a is k;
attribute a of e : entity is x;
attribute a : t;
disconnect s : t after 10 ns;
use foo.bar;
group G1 : E (L2);
group g is (signal);
assert c;
assume c;
assume_guarantee c;
restrict c;
restrict_guarantee c;
cover c;
fairness c;
strong fairness c,c;
property p is (a -> b);
sequence s is {c};
default clock is rising_edge(clk);
end entity;

@ -0,0 +1,36 @@
entity e is
generic (k:t);
generic map (k);
-- ^ error.illegal.map_aspect.generic
port (s:t);
port map (s);
-- ^ error.illegal.map_aspect.port
end entity;
entity e is
generic (k:t);
generic (k:t);
-- ^ error.repeated.clause.generic
end entity;
entity e is
port (s:t);
port (s:t);
-- ^ error.repeated.clause.port
end entity;
entity e is
port (s:t);
generic (k:t);
-- ^ error.order.generic_after_port
end entity;
entity e is
generic (k:t)
-- ^ error.missing.semicolon.after_clause
port (s:t)
-- ^ error.missing.semicolon.after_clause
end entity;

@ -0,0 +1,83 @@
entity e is
begin
process
begin
t <= x;
-- ^ error.illegal.assignment.in_passive_process
t <= force x;
-- ^ error.illegal.assignment.in_passive_process
t <= release;
-- ^ error.illegal.assignment.in_passive_process
end process;
end entity;
entity e is
begin
L1: block
-- ^ error.illegal.statement
begin
end block;
L2: component unit;
-- ^ error.illegal.statement
t <= x;
-- ^ error.illegal.statement
t <= x when c;
-- ^ error.illegal.statement
with e select
-- ^ error.illegal.statement
t <= x when x;
G1: for i in r
-- ^ error.illegal.statement
generate
end generate;
G1: if c generate
-- ^ error.illegal.statement
end generate;
G1: case e generate
-- ^ error.illegal.statement
end generate;
property p is p1;
-- ^ error.illegal.statement
sequence s is s1;
-- ^ error.illegal.statement
default clock is x;
-- ^ error.illegal.statement
p(arg);
process
begin
end process;
assert x;
assume x;
assume_guarantee x;
restrict x;
restrict_guarantee x;
cover x;
fairness x;
strong fairness x,x;
end entity;

@ -0,0 +1,12 @@
type enum_t is (foo, foo);
-- ^ error.repeated.enumerator
type enum_t is ('0', '0');
-- ^ error.repeated.enumerator
type enum_t is (foo, '1', foo);
-- ^ error.repeated.enumerator
type enum_t is ('0', foo, '0');
-- ^ error.repeated.enumerator

@ -0,0 +1,40 @@
function f;
-- ^ error.missing.return
function f is
-- ^ error.missing.return
begin
end;
function f (k:t);
-- ^ error.missing.return
function f (k:t) is
-- ^ error.missing.return
begin
end;
function "+" (k:t) return t is
begin
end g;
-- ^ error.misspeling.designator
function f (k:t) return t is
begin
end procedure;
-- ^ error.misspeling.subprogram_kind
pure function f (k:t) return t is
begin
end pure function;
-- ^ error.unexpected.purity.at_end
function "and" return t;
function "foo" return t;
-- ^ error.illegal.operator_symbol

@ -0,0 +1,7 @@
function foo is new bar [t];
-- ^ error.missing.return
function "+" is new foo."+" [t,t, return t];
-- ^ error.unexpected.comma

@ -0,0 +1,31 @@
function p
parameter (
signal s : out t;
-- ^ error.illegal.mode
signal s : inout t;
-- ^ error.illegal.mode
signal s : buffer t;
-- ^ error.illegal.mode
signal s : linkage t
-- ^ error.illegal.mode
) return t;
function p
parameter (signal s : t := expr) return t;
-- ^ error.illegal.default_expression
function p
parameter (
variable v : t;
-- ^ error.illegal.interface.variable
file f : t;
-- ^ error.illegal.interface.file
type t;
-- ^ error.illegal.interface.type
procedure p;
-- ^ error.illegal.interface.procedure
function f return f;
-- ^ error.illegal.interface.function
package pkg is new l.pkg
-- ^ error.illegal.interface.package
) return t;

@ -0,0 +1,12 @@
type int_t is range 0 to 255.0;
-- ^ error.illegal.range
type int_t is range 255 downto 0.0;
-- ^ error.illegal.range
type int_t is range 1.0 to 255;
-- ^ error.illegal.range
type int_t is range 255.0 downto 0;
-- ^ error.illegal.range

@ -0,0 +1,4 @@
package body pkg is
end package body foo;
-- ^ error.misspeling.name

@ -0,0 +1,128 @@
package body pkg is
signal s : t;
-- ^ error.illegal.declaration
component c is
-- ^ error.illegal.declaration
end component;
for l : c
-- ^ error.illegal.declaration
use open;
disconnect s : t after 10 ns;
-- ^ error.illegal.declaration
assert c;
-- ^ error.illegal.declaration
assume c;
-- ^ error.illegal.declaration
assume_guarantee c;
-- ^ error.illegal.declaration
restrict c;
-- ^ error.illegal.declaration
restrict_guarantee c;
-- ^ error.illegal.declaration
cover c;
-- ^ error.illegal.declaration
fairness c;
-- ^ error.illegal.declaration
strong fairness c,c;
-- ^ error.illegal.declaration
property p is (a -> b);
-- ^ error.illegal.declaration
sequence s is {c};
-- ^ error.illegal.declaration
default clock is rising_edge(clk);
-- ^ error.illegal.declaration
procedure p;
procedure p is
begin
end procedure;
procedure p2 is new up;
function f return t is
begin
end function;
function f return t;
function f2 is new uf;
package pkg is
end;
package body pkg is
end;
package pkg2 is new upkg;
type t is range 0 to 7;
subtype st is t;
constant k : t;
variable s : t;
shared variable s : t;
file f : t;
alias a is k;
attribute a of e : entity is x;
attribute a : t;
use foo.bar;
group G1 : E (L2);
group g is (signal);
end package body;
procedure p is
package body pkg is
shared variable sv : t;
-- ^ error.unexpected.shared
end package body;
begin
end procedure;
process
package body pkg is
shared variable sv : t;
-- ^ error.unexpected.shared
end package body;
begin
end process;
type t is
protected body
package body pkg is
shared variable sv : t;
-- ^ error.unexpected.shared
end package body;
end protected body;

@ -0,0 +1,3 @@
package pkg is
end package foo;
-- ^ error.misspeling.name

@ -0,0 +1,173 @@
package pkg is
procedure p is
-- ^ error.illegal.declaration
begin
end procedure;
function f return t is
-- ^ error.illegal.declaration
begin
end function;
for l : c
-- ^ error.illegal.declaration
use open;
procedure p;
function f return t;
procedure p2 is new up;
function f2 is new uf;
package pkg is
end;
package body pkg is
end;
package pkg2 is new upkg;
type t is range 0 to 7;
subtype st is t;
constant k : t;
signal s : t;
variable s : t;
shared variable s : t;
file f : t;
alias a is k;
component c is
end component;
attribute a of e : entity is x;
attribute a : t;
disconnect s : t after 10 ns;
use foo.bar;
group G1 : E (L2);
group g is (signal);
assert c;
assume c;
assume_guarantee c;
restrict c;
restrict_guarantee c;
cover c;
fairness c;
strong fairness c,c;
property p is (a -> b);
sequence s is {c};
default clock is rising_edge(clk);
end package;
package pkg is
type t is
protected
end protected;
type t is
protected body
-- ^ error.illegal.declaration
end protected body;
end package;
procedure p is
package pkg is
shared variable sv : t;
-- ^ error.unexpected.shared
signal s : t;
-- ^ error.illegal.declaration
disconnect s : t after 10 ns;
-- ^ error.illegal.declaration
property p is (a -> b);
-- ^ error.illegal.declaration
sequence s is {c};
-- ^ error.illegal.declaration
default clock is rising_edge(clk);
-- ^ error.illegal.declaration
end package;
begin
end procedure;
process
package pkg is
shared variable sv : t;
-- ^ error.unexpected.shared
signal s : t;
-- ^ error.illegal.declaration
disconnect s : t after 10 ns;
-- ^ error.illegal.declaration
property p is (a -> b);
-- ^ error.illegal.declaration
sequence s is {c};
-- ^ error.illegal.declaration
default clock is rising_edge(clk);
-- ^ error.illegal.declaration
end package;
begin
end process;
type t is
protected body
package pkg is
shared variable sv : t;
-- ^ error.unexpected.shared
signal s : t;
-- ^ error.illegal.declaration
disconnect s : t after 10 ns;
-- ^ error.illegal.declaration
property p is (a -> b);
-- ^ error.illegal.declaration
sequence s is {c};
-- ^ error.illegal.declaration
default clock is rising_edge(clk);
-- ^ error.illegal.declaration
end package;
end protected body;

@ -0,0 +1,43 @@
package pkg is
generic (k:t);
generic map (k);
port (s:t);
-- ^ error.illegal.clause.port
port map (s);
-- ^ error.illegal.map_aspect.port
end package;
package pkg is
generic (k:t);
generic (k:t);
-- ^ error.repeated.clause.generic
end package;
package pkg is
generic (k:t);
generic map (k);
generic map (k);
-- ^ error.repeated.map_aspect.generic
end package;
package pkg is
generic map (k);
-- ^ error.missing.clause.generic
end package;
package pkg is
generic map (k);
generic (k:t);
-- ^ error.order.clause_after_map_aspect
end package;
package pkg is
generic (k:t)
-- ^ error.missing.semicolon.after_clause
generic map (k)
-- ^ error.missing.semicolon.after_map_aspect
end package;

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