mirror of https://github.com/Wilfred/difftastic/
87 lines
1.1 KiB
VHDL
87 lines
1.1 KiB
VHDL
entity e is
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variable s : t;
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-- ^ error.illegal.declaration
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component c is
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-- ^ error.illegal.declaration
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end component;
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for l : c
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-- ^ error.illegal.declaration
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use open;
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procedure p;
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function f return t;
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procedure p is
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begin
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end procedure;
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function f return t is
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begin
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end function;
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procedure p2 is new up;
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function f2 is new uf;
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package pkg is
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end;
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package body pkg is
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end;
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package pkg2 is new upkg;
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type t is range 0 to 7;
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subtype st is t;
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constant k : t;
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signal s : t;
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shared variable s : t;
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file f : t;
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alias a is k;
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attribute a of e : entity is x;
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attribute a : t;
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disconnect s : t after 10 ns;
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use foo.bar;
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group G1 : E (L2);
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group g is (signal);
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assert c;
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assume c;
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assume_guarantee c;
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restrict c;
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restrict_guarantee c;
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cover c;
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fairness c;
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strong fairness c,c;
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property p is (a -> b);
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sequence s is {c};
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default clock is rising_edge(clk);
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end entity;
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