mirror of https://github.com/Wilfred/difftastic/
84 lines
1.2 KiB
VHDL
84 lines
1.2 KiB
VHDL
entity e is
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begin
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process
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begin
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t <= x;
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-- ^ error.illegal.assignment.in_passive_process
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t <= force x;
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-- ^ error.illegal.assignment.in_passive_process
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t <= release;
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-- ^ error.illegal.assignment.in_passive_process
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end process;
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end entity;
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entity e is
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begin
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L1: block
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-- ^ error.illegal.statement
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begin
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end block;
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L2: component unit;
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-- ^ error.illegal.statement
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t <= x;
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-- ^ error.illegal.statement
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t <= x when c;
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-- ^ error.illegal.statement
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with e select
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-- ^ error.illegal.statement
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t <= x when x;
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G1: for i in r
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-- ^ error.illegal.statement
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generate
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end generate;
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G1: if c generate
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-- ^ error.illegal.statement
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end generate;
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G1: case e generate
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-- ^ error.illegal.statement
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end generate;
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property p is p1;
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-- ^ error.illegal.statement
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sequence s is s1;
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-- ^ error.illegal.statement
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default clock is x;
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-- ^ error.illegal.statement
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p(arg);
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process
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begin
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end process;
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assert x;
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assume x;
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assume_guarantee x;
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restrict x;
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restrict_guarantee x;
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cover x;
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fairness x;
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strong fairness x,x;
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end entity;
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