mirror of https://github.com/Wilfred/difftastic/
37 lines
627 B
VHDL
37 lines
627 B
VHDL
entity e is
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generic (k:t);
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generic map (k);
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-- ^ error.illegal.map_aspect.generic
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port (s:t);
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port map (s);
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-- ^ error.illegal.map_aspect.port
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end entity;
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entity e is
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generic (k:t);
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generic (k:t);
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-- ^ error.repeated.clause.generic
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end entity;
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entity e is
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port (s:t);
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port (s:t);
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-- ^ error.repeated.clause.port
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end entity;
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entity e is
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port (s:t);
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generic (k:t);
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-- ^ error.order.generic_after_port
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end entity;
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entity e is
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generic (k:t)
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-- ^ error.missing.semicolon.after_clause
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port (s:t)
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-- ^ error.missing.semicolon.after_clause
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end entity;
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