mirror of https://github.com/Wilfred/difftastic/
36 lines
752 B
VHDL
36 lines
752 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity blinky is
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port (
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clk: in std_logic;
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led: out std_logic_vector(3 downto 0)
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);
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end entity;
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architecture a of blinky is
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constant CLK_FREQ: positive := 48_000_000;
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signal counter1: unsigned(25 downto 0) := (others => '0');
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signal counter2: unsigned(1 downto 0) := (others => '0');
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begin
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process(clk)
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begin
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if rising_edge(clk) then
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if to_integer(counter1) = CLK_FREQ / 2 then
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counter2 <= counter2 + 1;
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counter1 <= (others => '0');
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else
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counter1 <= counter1 + 1;
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end if;
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end if;
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end process;
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process(counter2)
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begin
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for n in 0 to 3 loop
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led(n) <= '1' when to_integer(counter2) = n else '0';
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end loop;
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end process;
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end architecture;
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